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author
oclyke
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Merge branch 'master' into core-ble
2 parents 9864d52 + 3c7022f commit 20c77c9

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-5411
lines changed

22 files changed

+6116
-5411
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‎boards.txt

+7-7
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ artemis.build.f_cpu=48000000L
3838
artemis.build.core=arduino
3939
artemis.build.extra_flags=-DPART_apollo3 -DAM_PACKAGE_BGA -DAM_PART_APOLLO3
4040
artemis.build.includes="-I{build.variant.path}/config" "-I{build.variant.path}/bsp"
41-
artemis.build.preferred_export_format=axf
41+
artemis.build.preferred_export_format=bin
4242
artemis.build.defs=
4343
artemis.build.libs=
4444
artemis.menu.svl_baud.921600=921600
@@ -76,7 +76,7 @@ amap3redboard.build.core=arduino
7676
amap3redboard.build.includes="-I{build.variant.path}/config" "-I{build.variant.path}/bsp"
7777
amap3redboard.build.ldscript={build.variant.path}/linker_scripts/gcc/artemis_sbl_svl_app.ld
7878
amap3redboard.build.extra_flags=-DPART_apollo3 -DAM_PACKAGE_BGA -DAM_PART_APOLLO3
79-
amap3redboard.build.preferred_export_format=axf
79+
amap3redboard.build.preferred_export_format=bin
8080
amap3redboard.build.defs=
8181
amap3redboard.build.libs=
8282
amap3redboard.menu.svl_baud.921600=921600
@@ -113,7 +113,7 @@ amap3nano.build.core=arduino
113113
amap3nano.build.includes="-I{build.variant.path}/config" "-I{build.variant.path}/bsp"
114114
amap3nano.build.ldscript={build.variant.path}/linker_scripts/gcc/artemis_sbl_svl_app.ld
115115
amap3nano.build.extra_flags=-DPART_apollo3 -DAM_PACKAGE_BGA -DAM_PART_APOLLO3
116-
amap3nano.build.preferred_export_format=axf
116+
amap3nano.build.preferred_export_format=bin
117117
amap3nano.build.defs=
118118
amap3nano.build.libs=
119119
amap3nano.menu.svl_baud.921600=921600
@@ -150,7 +150,7 @@ amap3atp.build.core=arduino
150150
amap3atp.build.includes="-I{build.variant.path}/config" "-I{build.variant.path}/bsp"
151151
amap3atp.build.extra_flags=-DPART_apollo3 -DAM_PACKAGE_BGA -DAM_PART_APOLLO3
152152
amap3atp.build.ldscript={build.variant.path}/linker_scripts/gcc/artemis_sbl_svl_app.ld
153-
amap3atp.build.preferred_export_format=axf
153+
amap3atp.build.preferred_export_format=bin
154154
amap3atp.build.defs=
155155
amap3atp.build.libs=
156156
amap3atp.menu.svl_baud.921600=921600
@@ -187,7 +187,7 @@ amap3thing.build.core=arduino
187187
amap3thing.build.includes="-I{build.variant.path}/config" "-I{build.variant.path}/bsp"
188188
amap3thing.build.ldscript={build.variant.path}/linker_scripts/gcc/artemis_sbl_svl_app.ld
189189
amap3thing.build.extra_flags=-DPART_apollo3 -DAM_PACKAGE_BGA -DAM_PART_APOLLO3
190-
amap3thing.build.preferred_export_format=axf
190+
amap3thing.build.preferred_export_format=bin
191191
amap3thing.build.defs=
192192
amap3thing.build.libs=
193193
amap3thing.menu.svl_baud.921600=921600
@@ -226,7 +226,7 @@ edge.build.includes="-I{build.variant.path}/config" "-I{build.variant.path}/bsp"
226226
edge.build.libs=
227227
edge.build.extra_flags=-DPART_apollo3 -DAM_PACKAGE_BGA -DAM_PART_APOLLO3
228228
edge.build.ldscript={build.variant.path}/linker_scripts/gcc/ambiq_sbl_app.ld
229-
edge.build.preferred_export_format=axf
229+
edge.build.preferred_export_format=bin
230230

231231
edge.menu.sbl_baud.921600=921600 (Default)
232232
edge.menu.sbl_baud.115200=115200 (TensorFlow Conference Versions)
@@ -271,7 +271,7 @@ edge2.build.core=arduino
271271
edge2.build.includes="-I{build.variant.path}/config" "-I{build.variant.path}/bsp"
272272
edge2.build.extra_flags=-DPART_apollo3 -DAM_PACKAGE_BGA -DAM_PART_APOLLO3
273273
edge2.build.ldscript={build.variant.path}/linker_scripts/gcc/artemis_sbl_svl_app.ld
274-
edge2.build.preferred_export_format=axf
274+
edge2.build.preferred_export_format=bin
275275
edge2.build.defs=
276276
edge2.build.libs=
277277
edge2.menu.svl_baud.921600=921600

‎cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Include/apollo3.h

+5,175-5,106
Large diffs are not rendered by default.

‎cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Include/system_apollo3.h

+7-7
Original file line numberDiff line numberDiff line change
@@ -8,26 +8,26 @@
88

99
//*****************************************************************************
1010
//
11-
// Copyright (c) 2019, Ambiq Micro
11+
// Copyright (c) 2020, Ambiq Micro
1212
// All rights reserved.
13-
//
13+
//
1414
// Redistribution and use in source and binary forms, with or without
1515
// modification, are permitted provided that the following conditions are met:
16-
//
16+
//
1717
// 1. Redistributions of source code must retain the above copyright notice,
1818
// this list of conditions and the following disclaimer.
19-
//
19+
//
2020
// 2. Redistributions in binary form must reproduce the above copyright
2121
// notice, this list of conditions and the following disclaimer in the
2222
// documentation and/or other materials provided with the distribution.
23-
//
23+
//
2424
// 3. Neither the name of the copyright holder nor the names of its
2525
// contributors may be used to endorse or promote products derived from this
2626
// software without specific prior written permission.
27-
//
27+
//
2828
// Third party software included in this distribution is subject to the
2929
// additional license terms as defined in the /docs/licenses directory.
30-
//
30+
//
3131
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
3232
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
3333
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

‎cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl.c

+127-26
Original file line numberDiff line numberDiff line change
@@ -13,26 +13,26 @@
1313

1414
//*****************************************************************************
1515
//
16-
// Copyright (c) 2019, Ambiq Micro
16+
// Copyright (c) 2020, Ambiq Micro
1717
// All rights reserved.
18-
//
18+
//
1919
// Redistribution and use in source and binary forms, with or without
2020
// modification, are permitted provided that the following conditions are met:
21-
//
21+
//
2222
// 1. Redistributions of source code must retain the above copyright notice,
2323
// this list of conditions and the following disclaimer.
24-
//
24+
//
2525
// 2. Redistributions in binary form must reproduce the above copyright
2626
// notice, this list of conditions and the following disclaimer in the
2727
// documentation and/or other materials provided with the distribution.
28-
//
28+
//
2929
// 3. Neither the name of the copyright holder nor the names of its
3030
// contributors may be used to endorse or promote products derived from this
3131
// software without specific prior written permission.
32-
//
32+
//
3333
// Third party software included in this distribution is subject to the
3434
// additional license terms as defined in the /docs/licenses directory.
35-
//
35+
//
3636
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
3737
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
3838
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -45,7 +45,7 @@
4545
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
4646
// POSSIBILITY OF SUCH DAMAGE.
4747
//
48-
// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package.
48+
// This is part of revision 2.4.1 of the AmbiqSuite Development Package.
4949
//
5050
//*****************************************************************************
5151

@@ -125,95 +125,113 @@ const struct
125125
uint32_t ui32MemoryEvent;
126126
uint32_t ui32MemoryMask;
127127
uint32_t ui32StatusMask;
128+
uint32_t ui32PwdSlpEnable;
128129
}
129130
am_hal_pwrctrl_memory_control[AM_HAL_PWRCTRL_MEM_MAX] =
130131
{
131-
{0, 0, 0},
132+
{0, 0, 0, 0, 0, 0},
132133
{AM_HAL_PWRCTRL_MEMEN_SRAM_8K_DTCM,
133134
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K_DTCM,
134135
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_8K_DTCM,
135136
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
136-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
137+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
138+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_8K_DTCM},
137139
{AM_HAL_PWRCTRL_MEMEN_SRAM_32K_DTCM,
138140
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K_DTCM,
139141
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_32K_DTCM,
140142
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
141-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
143+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
144+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_32K_DTCM},
142145
{AM_HAL_PWRCTRL_MEMEN_SRAM_64K_DTCM,
143146
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K_DTCM,
144147
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_64K_DTCM,
145148
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
146-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
149+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
150+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_64K_DTCM},
147151
{AM_HAL_PWRCTRL_MEMEN_SRAM_96K,
148152
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K,
149153
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_96K,
150154
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
151-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
155+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
156+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_96K},
152157
{AM_HAL_PWRCTRL_MEMEN_SRAM_128K,
153158
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K,
154159
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_128K,
155160
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
156-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
161+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
162+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_128K},
157163
{AM_HAL_PWRCTRL_MEMEN_SRAM_160K,
158164
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K,
159165
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_160K,
160166
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
161-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
167+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
168+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_160K},
162169
{AM_HAL_PWRCTRL_MEMEN_SRAM_192K,
163170
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K,
164171
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_192K,
165172
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
166-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
173+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
174+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_192K},
167175
{AM_HAL_PWRCTRL_MEMEN_SRAM_224K,
168176
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K,
169177
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_224K,
170178
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
171-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
179+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
180+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_224K},
172181
{AM_HAL_PWRCTRL_MEMEN_SRAM_256K,
173182
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K,
174183
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_256K,
175184
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
176-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
185+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
186+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_256K},
177187
{AM_HAL_PWRCTRL_MEMEN_SRAM_288K,
178188
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_288K,
179189
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_288K,
180190
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
181-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
191+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
192+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_288K},
182193
{AM_HAL_PWRCTRL_MEMEN_SRAM_320K,
183194
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_320K,
184195
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_320K,
185196
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
186-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
197+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
198+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_320K},
187199
{AM_HAL_PWRCTRL_MEMEN_SRAM_352K,
188200
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_352K,
189201
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_352K,
190202
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
191-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
203+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
204+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_352K},
192205
{AM_HAL_PWRCTRL_MEMEN_SRAM_384K,
193206
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_384K,
194207
AM_HAL_PWRCTRL_MEMPWREVENTEN_SRAM_384K,
195208
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
196-
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK},
209+
AM_HAL_PWRCTRL_MEM_REGION_SRAM_MASK,
210+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_SRAM_384K},
197211
{AM_HAL_PWRCTRL_MEMEN_FLASH_512K,
198212
AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_512K,
199213
AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_512K,
200214
AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK,
201-
AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK},
215+
AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK,
216+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_512K},
202217
{AM_HAL_PWRCTRL_MEMEN_FLASH_1M,
203218
AM_HAL_PWRCTRL_PWRONSTATUS_FLASH_1M,
204219
AM_HAL_PWRCTRL_MEMPWREVENTEN_FLASH_1M,
205220
AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK,
206-
AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK},
221+
AM_HAL_PWRCTRL_MEM_REGION_FLASH_MASK,
222+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_FLASH_1M},
207223
{AM_HAL_PWRCTRL_MEMEN_CACHE,
208224
0,
209225
AM_HAL_PWRCTRL_MEMPWREVENTEN_CACHE,
210226
AM_HAL_PWRCTRL_MEM_REGION_CACHE_MASK,
211-
0},
227+
0,
228+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_CACHE},
212229
{AM_HAL_PWRCTRL_MEMEN_ALL,
213230
AM_HAL_PWRCTRL_PWRONSTATUS_ALL,
214231
AM_HAL_PWRCTRL_MEMPWREVENTEN_ALL,
215232
AM_HAL_PWRCTRL_MEM_REGION_ALL_MASK,
216-
AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK}
233+
AM_HAL_PWRCTRL_MEM_REGION_ALT_ALL_MASK,
234+
AM_HAL_PWRCTRL_MEMPWDINSLEEP_ALL}
217235
};
218236

219237
// ****************************************************************************
@@ -441,6 +459,50 @@ am_hal_pwrctrl_memory_enable(am_hal_pwrctrl_mem_e eMemConfig)
441459
}
442460
}
443461

462+
// ****************************************************************************
463+
//
464+
// am_hal_pwrctrl_memory_deepsleep_powerdown()
465+
// Power down respective memory.
466+
//
467+
// ****************************************************************************
468+
uint32_t
469+
am_hal_pwrctrl_memory_deepsleep_powerdown(am_hal_pwrctrl_mem_e eMemConfig)
470+
{
471+
if ( eMemConfig >= AM_HAL_PWRCTRL_MEM_MAX )
472+
{
473+
return AM_HAL_STATUS_FAIL;
474+
}
475+
476+
//
477+
// Power down the required memory.
478+
//
479+
PWRCTRL->MEMPWDINSLEEP |= am_hal_pwrctrl_memory_control[eMemConfig].ui32PwdSlpEnable;
480+
481+
return AM_HAL_STATUS_SUCCESS;
482+
}
483+
484+
// ****************************************************************************
485+
//
486+
// am_hal_pwrctrl_memory_deepsleep_retain()
487+
// Apply retention voltage to respective memory.
488+
//
489+
// ****************************************************************************
490+
uint32_t
491+
am_hal_pwrctrl_memory_deepsleep_retain(am_hal_pwrctrl_mem_e eMemConfig)
492+
{
493+
if ( eMemConfig >= AM_HAL_PWRCTRL_MEM_MAX )
494+
{
495+
return AM_HAL_STATUS_FAIL;
496+
}
497+
498+
//
499+
// Retain the required memory.
500+
//
501+
PWRCTRL->MEMPWDINSLEEP &= ~am_hal_pwrctrl_memory_control[eMemConfig].ui32PwdSlpEnable;
502+
503+
return AM_HAL_STATUS_SUCCESS;
504+
}
505+
444506
// ****************************************************************************
445507
//
446508
// am_hal_pwrctrl_low_power_init()
@@ -472,6 +534,29 @@ am_hal_pwrctrl_low_power_init(void)
472534
}
473535
}
474536

537+
//
538+
// Adjust the SIMOBUCK LP settings.
539+
//
540+
if (APOLLO3_GE_B0)
541+
{
542+
MCUCTRL->SIMOBUCK2_b.SIMOBUCKCORELPHIGHTONTRIM = 2;
543+
MCUCTRL->SIMOBUCK2_b.SIMOBUCKCORELPLOWTONTRIM = 3;
544+
MCUCTRL->SIMOBUCK3_b.SIMOBUCKCORELPHIGHTOFFTRIM = 5;
545+
MCUCTRL->SIMOBUCK3_b.SIMOBUCKCORELPLOWTOFFTRIM = 2;
546+
MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPHIGHTOFFTRIM = 6;
547+
MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPLOWTOFFTRIM = 1;
548+
MCUCTRL->SIMOBUCK3_b.SIMOBUCKMEMLPHIGHTONTRIM = 3;
549+
MCUCTRL->SIMOBUCK4_b.SIMOBUCKMEMLPLOWTONTRIM = 3;
550+
}
551+
552+
//
553+
// Adjust the SIMOBUCK Timeout settings.
554+
//
555+
if (APOLLO3_GE_A1)
556+
{
557+
MCUCTRL->SIMOBUCK4_b.SIMOBUCKCOMP2TIMEOUTEN = 0;
558+
}
559+
475560
//
476561
// Configure cache for low power and performance.
477562
//
@@ -528,6 +613,22 @@ am_hal_pwrctrl_low_power_init(void)
528613
return AM_HAL_STATUS_SUCCESS;
529614
}
530615

616+
void am_hal_pwrctrl_blebuck_trim(void)
617+
{
618+
//
619+
// Enable the BLE buck trim values
620+
//
621+
if ( APOLLO3_GE_A1 )
622+
{
623+
AM_CRITICAL_BEGIN
624+
MCUCTRL->BLEBUCK2_b.BLEBUCKTONHITRIM = 0x19;
625+
MCUCTRL->BLEBUCK2_b.BLEBUCKTONLOWTRIM = 0xC;
626+
CLKGEN->BLEBUCKTONADJ_b.TONADJUSTEN = CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS;
627+
AM_CRITICAL_END
628+
}
629+
630+
}
631+
531632
//*****************************************************************************
532633
//
533634
// End Doxygen group.

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