Changes from Peter's feedback

Author: RiceShelley

lambdalib/ramlib/make.py

@@ -21,14 +21,14 @@
  ****************************************************************************/
 
 module la_asyncfifo #(
-    parameter DW    = 32,                  // Memory width
-    parameter DEPTH = 4,                   // FIFO depth
-    parameter ALMOST_FULL_LEVEL = DEPTH-1, // FIFO depth
-    parameter NS    = 1,                   // Number of power supplies
-    parameter CTRLW = 1,                   // width of asic ctrl interface
-    parameter TESTW = 1,                   // width of asic teset interface
-    parameter CHAOS = 0,                   // generates random full logic when set
-    parameter PROP  = "DEFAULT"            // Pass through variable for hard macro
+    parameter DW                = 32,       // Memory width
+    parameter DEPTH             = 4,        // FIFO depth
+    parameter ALMOST_FULL_LEVEL = DEPTH-1,  // FIFO depth
+    parameter NS                = 1,        // Number of power supplies
+    parameter CTRLW             = 1,        // width of asic ctrl interface
+    parameter TESTW             = 1,        // width of asic teset interface
+    parameter CHAOS             = 0,        // generates random full logic when set
+    parameter PROP              = "DEFAULT" // Pass through variable for hard macro
 ) (  // write port
     input                  wr_clk,
     input                  wr_nreset,

lambdalib/ramlib/rtl/la_asyncfifo.v

@@ -1,5 +1,3 @@
-import logging
-
 import cocotb
 from cocotb.triggers import RisingEdge
 from cocotb_bus.bus import Bus
@@ -8,6 +6,7 @@
 
 
 class LaAsyncFifoWrBus(Bus):
+    """Cocotb bus for lambdalib async FIFO WR interface"""
 
     _signals = ["wr_din", "wr_en", "wr_full"]
     _optional_signals = ["wr_almost_full", "wr_chaosmode"]
@@ -31,6 +30,7 @@ def from_prefix(cls, entity, prefix, **kwargs):
 
 
 class LaAsyncFifoRdBus(Bus):
+    """Cocotb bus for lambdalib async FIFO RD interface"""
 
     _signals = ["rd_dout", "rd_en", "rd_empty"]
     _optional_signals = []
@@ -60,7 +60,6 @@ def __init__(self, bus: LaAsyncFifoWrBus, clock, reset=None):
         self.bus = bus
         self.clock = clock
         self.reset = reset
-        self.log = logging.getLogger(f"cocotb.{bus._entity._name}.{bus._name}")
 
         self.queue = Queue()
         self.width = len(self.bus.wr_din)
@@ -113,7 +112,6 @@ def __init__(self, bus: LaAsyncFifoRdBus, clock, reset=None):
         self.bus = bus
         self.clock = clock
         self.reset = reset
-        self.log = logging.getLogger(f"cocotb.{bus._entity._name}.{bus._name}")
 
         self.queue = Queue()
         self.width = len(self.bus.rd_dout)
@@ -145,12 +143,13 @@ async def _run(self):
             await clock_edge_event
 
             fifo_empty = self.bus.rd_empty.value
-            if self.rd_en_generator:
+
+            if self._pause:
+                self.bus.rd_en.value = 0
+            elif self.rd_en_generator:
                 self.bus.rd_en.value = next(self.rd_en_generator)
-            elif not self._pause:
-                self.bus.rd_en.value = 1
             else:
-                self.bus.rd_en.value = 0
+                self.bus.rd_en.value = 1
 
             if self.bus.rd_en.value and not fifo_empty:
                 self.queue.put_nowait(self.bus.rd_dout.value)

lambdalib/ramlib/tests/la_asyncfifo.py

@@ -1,16 +1,20 @@
 import random
+from decimal import Decimal
+
+import siliconcompiler
 
 import cocotb
 from cocotb.clock import Clock
 from cocotb.triggers import ClockCycles, Timer, Combine
 from cocotb.regression import TestFactory
 from cocotb import utils
 
-from lambdalib.ramlib.tests.common import (
+from lambdalib import ramlib
+from lambdalib.utils._tb_common import (
+    run_cocotb,
     drive_reset,
     random_bool_generator
 )
-
 from lambdalib.ramlib.tests.la_asyncfifo import (
     LaAsyncFifoWrBus,
     LaAsyncFifoRdBus,
@@ -136,16 +140,51 @@ async def fifo_rd_wr_test(
 RAND_WR_CLK_PERIOD_NS, RAND_RD_CLK_PERIOD_NS = [utils.get_time_from_sim_steps(
     # Time step must be even for cocotb clock driver
     steps=utils.get_sim_steps(
-        time=MIN_PERIOD_NS + ((MAX_PERIOD_NS - MIN_PERIOD_NS) * random.random()),
+        time=Decimal(MIN_PERIOD_NS) + (
+            Decimal(MAX_PERIOD_NS - MIN_PERIOD_NS)
+            * Decimal(random.random()).quantize(Decimal("0.00"))
+        ),
         units="ns",
         round_mode="round"
     ) & ~1,
     units="ns"
 ) for _ in range(0, 2)]
 
+utils.get_sim_steps(Decimal("8.104"), "ns")
+
+# Factory to automatically generate a set of tests based on the different permutations
+# of the provided test arguments
 tf = TestFactory(fifo_rd_wr_test)
 tf.add_option('wr_clk_period_ns', [MIN_PERIOD_NS, RAND_WR_CLK_PERIOD_NS, MAX_PERIOD_NS])
 tf.add_option('rd_clk_period_ns', [MIN_PERIOD_NS, RAND_RD_CLK_PERIOD_NS, MAX_PERIOD_NS])
 tf.add_option('wr_en_generator', [None, random_bool_generator, bursty_en_gen])
 tf.add_option('rd_en_generator', [None, random_bool_generator, bursty_en_gen])
 tf.generate_tests()
+
+
+def test_la_asyncfifo():
+    chip = siliconcompiler.Chip("la_asyncfifo")
+
+    # TODO: Ask Peter how to set la_asyncfifo path
+    # such that it can be found by pytest and when run locally
+    chip.input("../rtl/la_asyncfifo.v")
+    chip.use(ramlib)
+
+    for depth in [2, 4, 8]:
+        test_module_name = "lambdalib.ramlib.tests.tb_la_asyncfifo"
+        test_name = f"{test_module_name}_depth_{depth}"
+        tests_failed = run_cocotb(
+            chip=chip,
+            test_module_name=test_module_name,
+            timescale=("1ns", "1ps"),
+            parameters={
+                "DW": 32,
+                "DEPTH": depth
+            },
+            output_dir_name=test_name
+        )
+        assert (tests_failed == 0), f"Error test {test_name} failed!"
+
+
+if __name__ == "__main__":
+    test_la_asyncfifo()

lambdalib/ramlib/tests/tb_la_asyncfifo.py

@@ -7,7 +7,7 @@
 from cocotb.runner import get_runner, get_results
 
 import siliconcompiler
-from siliconcompiler.tools.surelog import parse
+from siliconcompiler.tools.slang import elaborate
 
 
 def run_cocotb(
@@ -18,29 +18,26 @@ def run_cocotb(
         timescale=None,
         parameters=None):
 
-    print(f"test module name = {test_module_name}")
-
     # Use surelog to pickle Verilog sources
     flow = "cocotb_flow"
-    chip.node(flow, "import", parse)
+    chip.node(flow, "import", elaborate)
     chip.set("option", "flow", flow)
-    chip.run()
+    assert chip.run()
 
     pickled_verilog = chip.find_result("v", "import")
-    if not pickled_verilog:
-        assert False, "Could not locate pickled verilog"
+    assert pickled_verilog, "Could not locate pickled verilog"
 
     if output_dir_name is None:
         output_dir_name = test_module_name
 
-    pytest_current_test = os.getenv("PYTEST_CURRENT_TEST", None)
-
-    top_level_dir = Path(chip.getbuilddir()).parent.parent
+    top_level_dir = os.getcwd()
     build_dir = Path(chip.getbuilddir()) / output_dir_name
     test_dir = None
 
     results_xml = None
-    if not pytest_current_test:
+    # Need to check if we are running inside of pytest. See link below.
+    # https://github.com/cocotb/cocotb/blob/d883ce914063c3601455d10a40f459fffa22d8f2/cocotb/runner.py#L313 
+    if not os.getenv("PYTEST_CURRENT_TEST", None):
         results_xml = build_dir / "results.xml"
         test_dir = top_level_dir
 
@@ -56,7 +53,7 @@ def run_cocotb(
     )
     # Run test
     _, tests_failed = get_results(runner.test(
-        hdl_toplevel=chip.design,
+        hdl_toplevel=chip.top(),
         test_module=test_module_name,
         test_dir=test_dir,
         results_xml=results_xml,

lambdalib/ramlib/tests/test_pytest_runners.py

@@ -0,0 +1,8 @@
+import pytest
+
+import lambdalib.ramlib.tests.tb_la_asyncfifo as ramlib_tests
+
+
+@pytest.mark.eda
+def test_la_asyncfifo():
+    ramlib_tests.test_la_asyncfifo()