update spram template

Author: gadfort

lambdalib/utils/__init__.py

@@ -1,20 +1,26 @@
 from jinja2 import Template
 import os
-import math
 from collections import OrderedDict
 
 
-def write_la_spram(fout, memories, control_signals=None, la_type='ram', minbits=None):
+def write_la_ram(fout,
+                 memories,
+                 control_signals=None,
+                 la_type='la_spram',
+                 minsize=None):
     template_path = os.path.abspath(os.path.join(os.path.dirname(__file__),
                                                  'templates',
-                                                 'la_spmemory.v'))
+                                                 f'{la_type}memory.v'))
 
     widths_table = []
     depths_table = []
     memory_port_map = {}
     selection_table = {}
     memory_inst_map = {}
 
+    if minsize is None:
+        minsize = 0
+
     for memory, info in memories.items():
         widths_table.append(
             (memory, info['DW'])
@@ -35,12 +41,6 @@ def write_la_spram(fout, memories, control_signals=None, la_type='ram', minbits=
     for aw, items in selection_table.items():
         selection_table[aw] = OrderedDict(sorted(items.items(), reverse=True))
 
-        if minbits is not None:
-            depth = 2**aw
-            dw = int(math.floor(minbits / depth))
-            if dw > 0:
-                selection_table[aw][dw] = "SOFT"
-    selection_table[min(selection_table.keys()) - 1] = {0: "SOFT"}
     widths_table.sort()
     depths_table.sort()
 
@@ -54,4 +54,5 @@ def write_la_spram(fout, memories, control_signals=None, la_type='ram', minbits=
         selection_table=selection_table,
         inst_map=memory_inst_map,
         port_mapping=memory_port_map,
-        control_signals=control_signals))
+        control_signals=control_signals,
+        minsize=minsize))

lambdalib/utils/templates/la_spmemory.v renamed to lambdalib/utils/templates/la_sprammemory.v

@@ -1,5 +1,5 @@
 /*****************************************************************************
- * Function: Single Port {{ type }}
+ * Function: Single Port Memory ({{ type }})
  * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
@@ -13,14 +13,14 @@
  * Advanced ASIC development should rely on complete functional models
  * supplied on a per macro basis.
  *
- * Technologoy specific implementations of "la_sp{{ type }}" would generally include
+ * Technologoy specific implementations of "{{ type }}" would generally include
  * one or more hardcoded instantiations of {{ type }} modules with a generate
  * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
  ****************************************************************************/
 
-module la_sp{{ type }}
+module {{ type }}
   #(parameter DW     = 32,          // Memory width
     parameter AW     = 10,          // Address width (derived)
     parameter PROP   = "DEFAULT",   // Pass through variable for hard macro
@@ -44,8 +44,11 @@ module la_sp{{ type }}
     input [TESTW-1:0] test // pass through ASIC test interface
     );
 
+    // Total number of bits
+    localparam TOTAL_BITS = (2 ** AW) * DW;
+
     // Determine which memory to select
-    localparam MEM_PROP = (PROP != "DEFAULT") ? PROP :{% for aw, dw_select in selection_table.items() %}
+    localparam MEM_PROP = (PROP != "DEFAULT") ? PROP :{% if minsize > 0 %} ({{ minsize }} >= TOTAL_BITS) ? "SOFT" :{% endif %}{% for aw, dw_select in selection_table.items() %}
       {% if loop.nextitem is defined %}(AW >= {{ aw }}) ? {% endif %}{% for dw, memory in dw_select.items() %}{% if loop.nextitem is defined %}(DW >= {{dw}}) ? {% endif %}"{{ memory}}"{% if loop.nextitem is defined %} : {% endif%}{% endfor %}{% if loop.nextitem is defined %} :{% else %};{% endif %}{% endfor %}
 
     localparam MEM_WIDTH = {% for memory, width in width_table %}