wip integration

Author: hero78119

ceno_zkvm/src/chip_handler/register.rs

@@ -1,10 +1,7 @@
 use ff_ext::ExtensionField;
 use gkr_iop::error::CircuitBuilderError;
 
-use crate::{
-    circuit_builder::CircuitBuilder, gadgets::AssertLtConfig,
-    instructions::riscv::constants::UINT_LIMBS, structs::RAMType,
-};
+use crate::{circuit_builder::CircuitBuilder, gadgets::AssertLtConfig, structs::RAMType};
 use multilinear_extensions::{Expression, ToExpr};
 
 use super::{RegisterChipOperations, RegisterExpr};
@@ -20,39 +17,7 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
         ts: Expression<E>,
         value: RegisterExpr<E>,
     ) -> Result<(Expression<E>, AssertLtConfig), CircuitBuilderError> {
-        self.namespace(name_fn, |cb| {
-            // READ (a, v, t)
-            let read_record = [
-                vec![RAMType::Register.into()],
-                vec![register_id.expr()],
-                value.to_vec(),
-                vec![prev_ts.clone()],
-            ]
-            .concat();
-            // Write (a, v, t)
-            let write_record = [
-                vec![RAMType::Register.into()],
-                vec![register_id.expr()],
-                value.to_vec(),
-                vec![ts.clone()],
-            ]
-            .concat();
-            cb.read_record(|| "read_record", RAMType::Register, read_record)?;
-            cb.write_record(|| "write_record", RAMType::Register, write_record)?;
-
-            // assert prev_ts < current_ts
-            let lt_cfg = AssertLtConfig::construct_circuit(
-                cb,
-                || "prev_ts < ts",
-                prev_ts,
-                ts.clone(),
-                UINT_LIMBS,
-            )?;
-
-            let next_ts = ts + 1;
-
-            Ok((next_ts, lt_cfg))
-        })
+        self.ram_type_read(name_fn, RAMType::Register, register_id, prev_ts, ts, value)
     }
 
     fn register_write(
@@ -64,50 +29,14 @@ impl<E: ExtensionField, NR: Into<String>, N: FnOnce() -> NR> RegisterChipOperati
         prev_values: RegisterExpr<E>,
         value: RegisterExpr<E>,
     ) -> Result<(Expression<E>, AssertLtConfig), CircuitBuilderError> {
-        assert!(register_id.expr().degree() <= 1);
-        self.namespace(name_fn, |cb| {
-            // READ (a, v, t)
-            let read_record = [
-                vec![RAMType::Register.into()],
-                vec![register_id.expr()],
-                prev_values.to_vec(),
-                vec![prev_ts.clone()],
-            ]
-            .concat();
-            // Write (a, v, t)
-            let write_record = [
-                vec![RAMType::Register.into()],
-                vec![register_id.expr()],
-                value.to_vec(),
-                vec![ts.clone()],
-            ]
-            .concat();
-            cb.read_record(|| "read_record", RAMType::Register, read_record)?;
-            cb.write_record(|| "write_record", RAMType::Register, write_record)?;
-
-            let lt_cfg = AssertLtConfig::construct_circuit(
-                cb,
-                || "prev_ts < ts",
-                prev_ts,
-                ts.clone(),
-                UINT_LIMBS,
-            )?;
-
-            let next_ts = ts + 1;
-
-            #[cfg(test)]
-            {
-                use gkr_iop::circuit_builder::DebugIndex;
-                use itertools::izip;
-                use multilinear_extensions::power_sequence;
-                let pow_u16 = power_sequence((1 << u16::BITS as u64).into());
-                cb.register_debug_expr(
-                    DebugIndex::RdWrite as usize,
-                    izip!(value, pow_u16).map(|(v, pow)| v * pow).sum(),
-                );
-            }
-
-            Ok((next_ts, lt_cfg))
-        })
+        self.ram_type_write(
+            name_fn,
+            RAMType::Register,
+            register_id,
+            prev_ts,
+            ts,
+            prev_values,
+            value,
+        )
     }
 }

ceno_zkvm/src/circuit_builder.rs

@@ -2,21 +2,3 @@ pub type ConstraintSystem<E> = gkr_iop::circuit_builder::ConstraintSystem<E>;
 pub type NameSpace = gkr_iop::circuit_builder::NameSpace;
 pub type SetTableSpec = gkr_iop::circuit_builder::SetTableSpec;
 pub type CircuitBuilder<'a, E> = gkr_iop::circuit_builder::CircuitBuilder<'a, E>;
-
-// pub struct CircuitBuilder<'a, E: ExtensionField> {
-//     pub inner: gkr_iop::circuit_builder::CircuitBuilder<'a, E>,
-//     pub params: ProgramParams,
-// }
-
-// impl<'a, E: ExtensionField> Deref for CircuitBuilder<'a, E> {
-//     type Target = gkr_iop::circuit_builder::CircuitBuilder<'a, E>;
-//     fn deref(&self) -> &Self::Target {
-//         &self.inner
-//     }
-// }
-
-// impl<'a, E: ExtensionField> DerefMut for CircuitBuilder<'a, E> {
-//     fn deref_mut(&mut self) -> &mut Self::Target {
-//         &mut self.inner
-//     }
-// }

ceno_zkvm/src/instructions/riscv.rs

@@ -14,6 +14,7 @@ pub mod constants;
 pub mod div;
 pub mod dummy;
 pub mod ecall;
+pub mod ecall_base;
 pub mod jump;
 pub mod logic;
 pub mod logic_imm;