Ethernet Magnetics & Wiring

[sethp]

Given a schematic like:

We have the question: How ought we wire this into a PCB with a PHY chip and an RJ-45 jack?

I found what feels like a rich source of information looking for ethernet phy magnetics choke, including:

1. https://ww1.microchip.com/downloads/en/Appnotes/VPPD-01740.pdf —this is a nice high level summary of what magnetics are for and what problems they solve:

   While not explicitly required by IEEE 802.3, magnetics are the most commonly used method of meeting the requirements of the 10/100/1000BASE-T PMA electrical interface. However, there is no one standard configuration that meets all objectives for all designs at the lowest cost. Magnetics offer a straightforward solution to many functions of this interface, including electrical isolation, signal balancing, common-mode rejection, impedance matching, and EMC improvement. The following sections briefly describe each of these areas.

   as well as specific wiring guides for two different "magenetics" designs (including the one above; more on that later)

2. https://electronics.stackexchange.com/questions/286381/how-does-ethernet-magnetics-work —this feels appropriate to my (our?) novice level of RF isolation; the key insight for me is terminology:

   The first transformer (up down one) is an isolation transformer, it passes the high frequency signals that represent the bits of ethernet, but rejects DC.

   The second transformer is a common mode choke, it blocks signals that are common to both terminals and allows signals that are not common from both terminals to pass through

3. https://electronics.stackexchange.com/questions/404008/proper-connection-of-choke-coil-in-ethernet-magnetics —this starts off strong, asking "how do I wire up this particular part," and the answer (at least to me) was a bit opaque until I read the above. At that point, this started to make sense:

   The common mode chokes would serve no purpose on the PHY side, and I have seen no schematics with them on the PHY side. The PHY side actually must be as a clean as possible with just bias resistors at most. The PHY side drivers expect a very short connection directly to the magnetics. Designs vary so not all center taps are used.

4. And finally, https://electronics.stackexchange.com/questions/715699/why-are-common-mode-chokes-used-in-ethernet-magnetics —this one feels a bit aspirational to me; I recognize many of the words and concepts, but it's a slow & chunky read. Not clear if having the understanding makes this one clearer, or if this one clears up having the understanding. Something that seems relevant:

   Adding stub length at the PHY side is undesirable. There is a pretty generous margin to spare, here -- 10/100, and even 1000BASE-T, have quite low symbol rates, as "high speed" communications are concerned (down to ~8ns) -- so we can easily afford a fraction of a ns of stub length here or there. But it does add up, and we start with a minimum stub length in the transformer itself. Any PHY-side CMC [common mode choke], and trace length on the PCB, counts against us. [emphasis mine]

So it seems like for us the common-mode choke (labeled MX1+/MX1-) ought to "face" the RJ-45 jack, and the transformer (TD1+/TD1-) ought to be connected to the PHY chip.

What to do with the center taps is still less clear, since it seems to imply a variety of tradeoffs that I don't fully understand. Some designs connect them (through capacitors) to ground, some to "chassis ground" (AKA "shield"), still others use "Bob Smith" termination. About the only consistent thing I've found is that PoE (power over ethernet [cable]) makes use of the cable-facing center tap, and thus requires the common-mode choke to go on the opposite side.

Seems like the easiest thing to do is what's suggested by ENT-AN0098 (the first item above):

which with our schematic would suggest connecting MCT1 to SHIELD through a "Bob Smith" capacitor/resistor (a 75Ω resistor and a capacitor rated at 1000pF,2kV), and TCT1 to GND through a.... "smallish" capacitor? (not sure how to size "C1", there).

[dougli1sqrd]

https://electronics.stackexchange.com/questions/404008/proper-connection-of-choke-coil-in-ethernet-magnetics —this starts off strong, asking "how do I wire up this particular part," and the answer (at least to me) was a bit opaque until I read the above. At that point, this started to make sense:

Oh this is interesting bc I feel like I've seen ethernet RJ45 jacks with the choke facing in either direction. Like sometimes it faces the PHY, other times it faces the input. But I could be misremembering. But for a rule of thumb I think just doing what the above picture says sounds just fine to me

[sethp]

Yeah, "it depends"—further down in that same page there's some discussion about PoE:

In a PoE application, the positive DC power will be transmitted using any one or two pairs of the line. If common-mode choke is used on the cable side, it will try to reject this same voltage appearing on one of the pairs. So they have provided the CM chokes on the PHY side.
—https://electronics.stackexchange.com/a/586762/174014

But, as noted by the fourth link, putting the CMC on the PHY side spends out of the same budget as longer (/mismatched?) traces. So roughly the tradeoff space in my head right now is: CMC facing "outward" is easier, but costs the possibility of PoE (which we're not aiming for in this iteration anyway).

[sethp]

Oh, and by "easier" I should note that I mean "more likely to work with a wider range of PCB designs"; or, in other words, less likely to fail in a mysterious way given choices elsewhere.

There are also a handful of non-transformer ways to meet the standard's galvanic isolation requirements (https://en.wikipedia.org/wiki/Galvanic_isolation has a list, not that any are likely to be cheaper/easier than "magnetics"), and we could also even potentially consider just.... not meeting them. Given two devices connected with a very short cable and plugged into the same power strip, a lot of the noise & isolation-y bits just kinda... fall away, since the whole area will be bathed in the same interference anyway and there's no way to have (significant?) "ground loops"

Assuming https://resources.altium.com/p/gigabit-ethernet-101-basics-implementation#magnetics is a complete list, a magnetics-less design would essentially be borrowing from the engineering tolerances on both the GSW and whatever the peer's PHY layer looks like for "balancing"/"impedance matching", and we'd be vulnerable to ESD shocks. But maybe those are acceptable for a v0 prototype, too?

[sethp]

Trace Length Matching?

In a video discussion we talked about length matching as it relates to signal phase:

c = λ * f => 125MHz signal has wavelength of 1440mm in copper (where c ~ 0.6 * 300e6 m/s)

So we concluded a trace pair that was 1440mm longer than another would have its differential signal arrive about one full phase later. That'd definitely be wrong, but we weren't sure where "right" is: what phase ratio is an Ethernet PHY allowed to express?

Conservatively, we guessed somewhere between 5% and 1%. In terms of trace length, that implies keeping the a delta between differential pairs heading for the same RJ-45 jack to less than 72mm (for 5%) or 14.4mm (for 1%).