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uefi: Add (partial) safe protocol implementation for PCI_ROOT_BRIDGE_IO_PROTOCOL
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‎uefi/CHANGELOG.md

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## Added
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- Added `ConfigTableEntry::MEMORY_ATTRIBUTES_GUID` and `ConfigTableEntry::IMAGE_SECURITY_DATABASE_GUID`.
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- Added `proto::pci::PciRootBridgeIo`.
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## Changed
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- **Breaking:** `boot::stall` now take `core::time::Duration` instead of `usize`.

‎uefi/src/proto/mod.rs

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@@ -22,6 +22,7 @@ pub mod misc;
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pub mod network;
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#[cfg(feature = "alloc")]
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pub mod nvme;
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pub mod pci;
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pub mod pi;
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pub mod rng;
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#[cfg(feature = "alloc")]

‎uefi/src/proto/pci/mod.rs

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// SPDX-License-Identifier: MIT OR Apache-2.0
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//! PCI Bus specific protocols.
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use uefi_raw::protocol::pci::root_bridge::PciRootBridgeIoProtocolWidth;
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pub mod root_bridge;
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/// IO Address for PCI/register IO operations
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#[repr(C, packed)]
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub struct PciIoAddress {
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/// Register number within the PCI device.
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pub reg: u8,
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/// Function number within the PCI device.
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pub fun: u8,
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/// Device number within the PCI bus.
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pub dev: u8,
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/// Bus number in the PCI hierarchy.
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pub bus: u8,
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/// Extended register number within the PCI device.
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pub ext_reg: u32,
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}
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impl PciIoAddress {
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/// Create address pointing to the device identified by `bus`, `dev` and `fun` ids.
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#[must_use]
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pub const fn new(bus: u8, dev: u8, fun: u8) -> Self {
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Self {
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bus,
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dev,
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fun,
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reg: 0,
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ext_reg: 0,
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}
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}
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/// Configure the **byte**-offset of the register to access.
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#[must_use]
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pub const fn with_register(&self, reg: u8) -> Self {
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let mut addr = *self;
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addr.reg = reg;
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addr.ext_reg = 0;
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addr
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}
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/// Configure the **byte**-offset of the extended register to access.
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#[must_use]
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pub const fn with_extended_register(&self, ext_reg: u32) -> Self {
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let mut addr = *self;
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addr.reg = 0;
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addr.ext_reg = ext_reg;
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addr
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}
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}
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impl From<PciIoAddress> for u64 {
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fn from(value: PciIoAddress) -> Self {
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unsafe { core::mem::transmute(value) }
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}
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}
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/// Trait implemented by all data types that can natively be read from a PCI device.
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/// Note: Not all of them have to actually be supported by the hardware at hand.
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pub trait PciIoUnit: Sized + Default {}
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impl PciIoUnit for u8 {}
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impl PciIoUnit for u16 {}
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impl PciIoUnit for u32 {}
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impl PciIoUnit for u64 {}
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#[allow(dead_code)]
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enum PciIoMode {
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Normal,
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Fifo,
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Fill,
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}
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fn encode_io_mode_and_unit<U: PciIoUnit>(mode: PciIoMode) -> PciRootBridgeIoProtocolWidth {
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match (mode, core::mem::size_of::<U>()) {
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(PciIoMode::Normal, 1) => PciRootBridgeIoProtocolWidth::UINT8,
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(PciIoMode::Normal, 2) => PciRootBridgeIoProtocolWidth::UINT16,
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(PciIoMode::Normal, 4) => PciRootBridgeIoProtocolWidth::UINT32,
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(PciIoMode::Normal, 8) => PciRootBridgeIoProtocolWidth::UINT64,
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(PciIoMode::Fifo, 1) => PciRootBridgeIoProtocolWidth::FIFO_UINT8,
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(PciIoMode::Fifo, 2) => PciRootBridgeIoProtocolWidth::FIFO_UINT16,
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(PciIoMode::Fifo, 4) => PciRootBridgeIoProtocolWidth::FIFO_UINT32,
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(PciIoMode::Fifo, 8) => PciRootBridgeIoProtocolWidth::FIFO_UINT64,
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(PciIoMode::Fill, 1) => PciRootBridgeIoProtocolWidth::FILL_UINT8,
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(PciIoMode::Fill, 2) => PciRootBridgeIoProtocolWidth::FILL_UINT16,
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(PciIoMode::Fill, 4) => PciRootBridgeIoProtocolWidth::FILL_UINT32,
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(PciIoMode::Fill, 8) => PciRootBridgeIoProtocolWidth::FILL_UINT64,
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_ => unreachable!("Illegal PCI IO-Mode / Unit combination"),
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}
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}

‎uefi/src/proto/pci/root_bridge.rs

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// SPDX-License-Identifier: MIT OR Apache-2.0
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//! PCI Root Bridge protocol.
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use core::ptr;
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use super::{PciIoAddress, PciIoUnit, encode_io_mode_and_unit};
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use crate::StatusExt;
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use uefi_macros::unsafe_protocol;
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use uefi_raw::protocol::pci::root_bridge::{PciRootBridgeIoAccess, PciRootBridgeIoProtocol};
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/// Protocol that provides access to the PCI Root Bridge I/O protocol.
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///
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/// # UEFI Spec Description
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/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are
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/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller.
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#[derive(Debug)]
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#[repr(transparent)]
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#[unsafe_protocol(PciRootBridgeIoProtocol::GUID)]
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pub struct PciRootBridgeIo(PciRootBridgeIoProtocol);
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impl PciRootBridgeIo {
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/// Get the segment number where this PCI root bridge resides.
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#[must_use]
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pub const fn segment_nr(&self) -> u32 {
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self.0.segment_number
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}
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/// Access PCI I/O operations on this root bridge.
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pub const fn pci(&mut self) -> PciIoAccessPci<'_> {
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PciIoAccessPci {
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proto: &mut self.0,
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io_access: &mut self.0.pci,
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}
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}
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/// Flush all PCI posted write transactions from a PCI host bridge to system memory.
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///
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/// # Errors
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/// - [`crate::Status::DEVICE_ERROR`] The PCI posted write transactions were not flushed from the PCI host bridge
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/// due to a hardware error.
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pub fn flush(&mut self) -> crate::Result<()> {
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unsafe { (self.0.flush)(&mut self.0).to_result() }
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}
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// TODO: poll I/O
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// TODO: mem I/O access
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// TODO: io I/O access
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// TODO: map & unmap & copy memory
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// TODO: buffer management
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// TODO: get/set attributes
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// TODO: configuration / resource settings
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}
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/// Struct for performing PCI I/O operations on a root bridge.
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#[derive(Debug)]
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pub struct PciIoAccessPci<'a> {
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proto: *mut PciRootBridgeIoProtocol,
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io_access: &'a mut PciRootBridgeIoAccess,
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}
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impl PciIoAccessPci<'_> {
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/// Reads a single value of type `U` from the specified PCI address.
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///
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/// # Arguments
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/// - `addr` - The PCI address to read from.
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///
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/// # Returns
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/// - The read value of type `U`.
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///
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/// # Errors
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/// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
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/// - [`crate::Status::OUT_OF_RESOURCES`] The read request could not be completed due to a lack of resources.
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pub fn read_one<U: PciIoUnit>(&self, addr: PciIoAddress) -> crate::Result<U> {
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let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Normal);
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let mut result = U::default();
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unsafe {
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(self.io_access.read)(
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self.proto,
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width_mode,
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addr.into(),
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1,
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ptr::from_mut(&mut result).cast(),
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)
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.to_result_with_val(|| result)
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}
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}
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/// Writes a single value of type `U` to the specified PCI address.
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///
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/// # Arguments
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/// - `addr` - The PCI address to write to.
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/// - `data` - The value to write.
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///
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/// # Errors
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/// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
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/// - [`crate::Status::OUT_OF_RESOURCES`] The write request could not be completed due to a lack of resources.
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pub fn write_one<U: PciIoUnit>(&self, addr: PciIoAddress, data: U) -> crate::Result<()> {
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let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Normal);
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unsafe {
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(self.io_access.write)(
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self.proto,
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width_mode,
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addr.into(),
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1,
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ptr::from_ref(&data).cast(),
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)
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.to_result()
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}
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}
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/// Reads multiple values from the specified PCI address range.
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///
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/// # Arguments
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/// - `addr` - The starting PCI address to read from.
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/// - `data` - A mutable slice to store the read values.
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///
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/// # Errors
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/// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
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/// - [`crate::Status::OUT_OF_RESOURCES`] The read operation could not be completed due to a lack of resources.
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pub fn read<U: PciIoUnit>(&self, addr: PciIoAddress, data: &mut [U]) -> crate::Result<()> {
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let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Normal);
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unsafe {
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(self.io_access.read)(
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self.proto,
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width_mode,
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addr.into(),
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data.len(),
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data.as_mut_ptr().cast(),
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)
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.to_result()
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}
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}
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/// Writes multiple values to the specified PCI address range.
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///
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/// # Arguments
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/// - `addr` - The starting PCI address to write to.
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/// - `data` - A slice containing the values to write.
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///
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/// # Errors
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/// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
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/// - [`crate::Status::OUT_OF_RESOURCES`] The write operation could not be completed due to a lack of resources.
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pub fn write<U: PciIoUnit>(&self, addr: PciIoAddress, data: &[U]) -> crate::Result<()> {
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let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Normal);
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unsafe {
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(self.io_access.write)(
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self.proto,
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width_mode,
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addr.into(),
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data.len(),
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data.as_ptr().cast(),
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)
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.to_result()
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}
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}
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/// Fills a PCI address range with the specified value.
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///
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/// # Arguments
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/// - `addr` - The starting PCI address to fill.
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/// - `count` - The number of units to write.
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/// - `data` - The value to fill the address range with.
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///
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/// # Errors
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/// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
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/// - [`crate::Status::OUT_OF_RESOURCES`] The operation could not be completed due to a lack of resources.
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pub fn fill_write<U: PciIoUnit>(
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&self,
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addr: PciIoAddress,
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count: usize,
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data: U,
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) -> crate::Result<()> {
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let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Fill);
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unsafe {
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(self.io_access.write)(
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self.proto,
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width_mode,
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addr.into(),
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count,
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ptr::from_ref(&data).cast(),
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)
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.to_result()
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}
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}
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/// Reads a sequence of values of type `U` from the specified PCI address by repeatedly accessing it.
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///
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/// # Arguments
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/// - `addr` - The PCI address to read from.
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/// - `data` - A mutable slice to store the read values.
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///
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/// # Behavior
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/// This reads from the same memory region (starting at `addr` and ending at `addr + size_of::<U>()`) repeatedly.
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/// The resulting `data` buffer will contain the elements returned by reading the same address multiple times sequentially.
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///
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/// # Errors
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/// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
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/// - [`crate::Status::OUT_OF_RESOURCES`] The read operation could not be completed due to a lack of resources.
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pub fn fifo_read<U: PciIoUnit>(&self, addr: PciIoAddress, data: &mut [U]) -> crate::Result<()> {
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let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Fifo);
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unsafe {
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(self.io_access.read)(
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self.proto,
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width_mode,
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addr.into(),
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data.len(),
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data.as_mut_ptr().cast(),
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)
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.to_result()
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}
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}
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/// Writes a sequence of values of type `U` to the specified PCI address repeatedly.
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///
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/// # Arguments
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/// - `addr` - The PCI address to write to.
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/// - `data` - A slice containing the values to write.
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///
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/// # Behavior
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/// This sequentially writes all elements within the given `data` buffer to the same memory region
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/// (starting at `addr` and ending at `addr + size_of::<U>()`) sequentially.
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///
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/// # Errors
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/// - [`crate::Status::INVALID_PARAMETER`] The requested width is invalid for this PCI root bridge.
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/// - [`crate::Status::OUT_OF_RESOURCES`] The write operation could not be completed due to a lack of resources.
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pub fn fifo_write<U: PciIoUnit>(&self, addr: PciIoAddress, data: &[U]) -> crate::Result<()> {
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let width_mode = encode_io_mode_and_unit::<U>(super::PciIoMode::Fifo);
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unsafe {
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(self.io_access.write)(
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self.proto,
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width_mode,
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addr.into(),
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data.len(),
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data.as_ptr().cast(),
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)
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.to_result()
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}
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}
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}

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