Implement automatic verification for ARM/AArch64 intrinsics (#626)

This commit implements automatic verification of implement ARM/AArch64
intrinsics. Or it's at least a start! This downloads a snapshot of ARM's
[online documentation][docs] and implements necessary logic to parse
that and use it to verify all the intrinsics. Almost everything
checked out A-OK but a few minor tweaks were needed to the neon
intrinsics and the crc ones needed some renaming.

[docs]: https://developer.arm.com/technologies/neon/intrinsics

Author: alexcrichton

coresimd/aarch64/crc.rs

@@ -25,63 +25,63 @@ use stdsimd_test::assert_instr;
 #[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32b))]
-pub unsafe fn crc32b(crc: u32, data: u8) -> u32 {
+pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 {
     crc32b_(crc, data as u32)
 }
 
 /// CRC32 single round checksum for half words (16 bits).
 #[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32h))]
-pub unsafe fn crc32h(crc: u32, data: u16) -> u32 {
+pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 {
     crc32h_(crc, data as u32)
 }
 
 /// CRC32 single round checksum for words (32 bits).
 #[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32w))]
-pub unsafe fn crc32w(crc: u32, data: u32) -> u32 {
+pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 {
     crc32w_(crc, data)
 }
 
 /// CRC32 single round checksum for quad words (64 bits).
 #[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32x))]
-pub unsafe fn crc32x(crc: u32, data: u64) -> u32 {
+pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
     crc32x_(crc, data)
 }
 
 /// CRC32-C single round checksum for bytes (8 bits).
 #[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32cb))]
-pub unsafe fn crc32cb(crc: u32, data: u8) -> u32 {
+pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 {
     crc32cb_(crc, data as u32)
 }
 
 /// CRC32-C single round checksum for half words (16 bits).
 #[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32ch))]
-pub unsafe fn crc32ch(crc: u32, data: u16) -> u32 {
+pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 {
     crc32ch_(crc, data as u32)
 }
 
 /// CRC32-C single round checksum for words (32 bits).
 #[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32cw))]
-pub unsafe fn crc32cw(crc: u32, data: u32) -> u32 {
+pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
     crc32cw_(crc, data)
 }
 
 /// CRC32-C single round checksum for quad words (64 bits).
 #[inline]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32cx))]
-pub unsafe fn crc32cx(crc: u32, data: u64) -> u32 {
+pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {
     crc32cx_(crc, data)
 }
 
@@ -94,50 +94,50 @@ mod tests {
 
     #[simd_test(enable = "crc")]
     unsafe fn test_crc32b() {
-        assert_eq!(crc32b(0, 0), 0);
-        assert_eq!(crc32b(0, 255), 755167117);
+        assert_eq!(__crc32b(0, 0), 0);
+        assert_eq!(__crc32b(0, 255), 755167117);
     }
 
     #[simd_test(enable = "crc")]
     unsafe fn test_crc32h() {
-        assert_eq!(crc32h(0, 0), 0);
-        assert_eq!(crc32h(0, 16384), 1994146192);
+        assert_eq!(__crc32h(0, 0), 0);
+        assert_eq!(__crc32h(0, 16384), 1994146192);
     }
 
     #[simd_test(enable = "crc")]
     unsafe fn test_crc32w() {
-        assert_eq!(crc32w(0, 0), 0);
-        assert_eq!(crc32w(0, 4294967295), 3736805603);
+        assert_eq!(__crc32w(0, 0), 0);
+        assert_eq!(__crc32w(0, 4294967295), 3736805603);
     }
 
     #[simd_test(enable = "crc")]
-    unsafe fn test_crc32x() {
-        assert_eq!(crc32x(0, 0), 0);
-        assert_eq!(crc32x(0, 18446744073709551615), 1147535477);
+    unsafe fn test_crc32d() {
+        assert_eq!(__crc32d(0, 0), 0);
+        assert_eq!(__crc32d(0, 18446744073709551615), 1147535477);
     }
 
     #[simd_test(enable = "crc")]
     unsafe fn test_crc32cb() {
-        assert_eq!(crc32cb(0, 0), 0);
-        assert_eq!(crc32cb(0, 255), 2910671697);
+        assert_eq!(__crc32cb(0, 0), 0);
+        assert_eq!(__crc32cb(0, 255), 2910671697);
     }
 
     #[simd_test(enable = "crc")]
     unsafe fn test_crc32ch() {
-        assert_eq!(crc32ch(0, 0), 0);
-        assert_eq!(crc32ch(0, 16384), 1098587580);
+        assert_eq!(__crc32ch(0, 0), 0);
+        assert_eq!(__crc32ch(0, 16384), 1098587580);
     }
 
     #[simd_test(enable = "crc")]
     unsafe fn test_crc32cw() {
-        assert_eq!(crc32cw(0, 0), 0);
-        assert_eq!(crc32cw(0, 4294967295), 3080238136);
+        assert_eq!(__crc32cw(0, 0), 0);
+        assert_eq!(__crc32cw(0, 4294967295), 3080238136);
     }
 
     #[simd_test(enable = "crc")]
-    unsafe fn test_crc32cx() {
-        assert_eq!(crc32cx(0, 0), 0);
-        assert_eq!(crc32cx(0, 18446744073709551615), 3293575501);
+    unsafe fn test_crc32cd() {
+        assert_eq!(__crc32cd(0, 0), 0);
+        assert_eq!(__crc32cd(0, 18446744073709551615), 3293575501);
     }
 
 }

coresimd/aarch64/neon.rs

@@ -9,6 +9,8 @@ use coresimd::simd_llvm::*;
 #[cfg(test)]
 use stdsimd_test::assert_instr;
 
+use mem;
+
 types! {
     /// ARM-specific 64-bit wide vector of one packed `f64`.
     pub struct float64x1_t(f64); // FIXME: check this!
@@ -250,16 +252,20 @@ pub unsafe fn vaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(add))]
-pub unsafe fn vaddd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
-    simd_add(a, b)
+pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 {
+    let a: int64x1_t = mem::transmute(a);
+    let b: int64x1_t = mem::transmute(b);
+    simd_extract(simd_add(a, b), 0)
 }
 
 /// Vector add.
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(add))]
-pub unsafe fn vaddd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
-    simd_add(a, b)
+pub unsafe fn vaddd_u64(a: u64, b: u64) -> u64 {
+    let a: uint64x1_t = mem::transmute(a);
+    let b: uint64x1_t = mem::transmute(b);
+    simd_extract(simd_add(a, b), 0)
 }
 
 /// Horizontal vector max.

coresimd/arm/neon.rs

@@ -702,7 +702,7 @@ pub unsafe fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vtbl))]
-pub unsafe fn vtbl1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
+pub unsafe fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
     ::mem::transmute(vtbl1(::mem::transmute(a), ::mem::transmute(b)))
 }
 

crates/stdsimd-verify/Cargo.toml

@@ -2,6 +2,7 @@
 name = "stdsimd-verify"
 version = "0.1.0"
 authors = ["Alex Crichton <[email protected]>"]
+edition = "2018"
 
 [dependencies]
 proc-macro2 = "0.4"
@@ -13,6 +14,6 @@ proc-macro = true
 test = false
 
 [dev-dependencies]
-serde = "1.0"
-serde_derive = "1.0"
+serde = { version = "1.0", features = ['derive'] }
 serde-xml-rs = "0.2"
+html5ever = "0.22.5"