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Document what the xcr0 masks do
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stdsimd/arch/detect/os/x86.rs

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@@ -151,13 +151,20 @@ fn detect_features() -> cache::Initializer {
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if cpu_osxsave {
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// 2. The OS must have signaled the CPU that it supports saving and
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// restoring the SSE and AVX registers by setting `XCR0.SSE[1]` and
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// `XCR0.AVX[2]` to `1`.
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// restoring the:
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//
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// * SSE -> `XCR0.SSE[1]`
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// * AVX -> `XCR0.AVX[2]`
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// * AVX-512 -> `XCR0.AVX-512[7:5]`.
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//
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// by setting the corresponding bits of `XCR0` to `1`.
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//
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// This is safe because the CPU supports `xsave`
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// and the OS has set `osxsave`.
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let xcr0 = unsafe { _xgetbv(0) };
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// Test `XCR0.SSE[1]` and `XCR0.AVX[2]` with the mask `0b110 == 6`:
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let os_avx_support = xcr0 & 6 == 6;
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// Test `XCR0.AVX-512[7:5]` with the mask `0b1110_0000 == 224`:
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let os_avx512_support = xcr0 & 224 == 224;
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// Only if the OS and the CPU support saving/restoring the AVX

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