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borsbors
committedSep 27, 2020
Auto merge of #77272 - jonas-schievink:rollup-dydo5kn, r=jonas-schievink
Rollup of 7 pull requests Successful merges: - #76839 (Add asm! support for MIPS) - #77203 (Check for missing const-stability attributes in `rustc_passes`) - #77249 (Separate `private_intra_doc_links` and `broken_intra_doc_links` into separate lints) - #77252 (reduce overlong line) - #77256 (Fix typo in ExpnData documentation) - #77262 (Remove duplicate comment) - #77263 (Clean up trivial if let) Failed merges: r? `@ghost`
2 parents 1d216fe + 344ab3f commit 4529af9

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‎compiler/rustc_codegen_llvm/src/asm.rs

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -259,6 +259,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
259259
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
260260
InlineAsmArch::Nvptx64 => {}
261261
InlineAsmArch::Hexagon => {}
262+
InlineAsmArch::Mips => {}
262263
}
263264
}
264265
if !options.contains(InlineAsmOptions::NOMEM) {
@@ -505,6 +506,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
505506
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
506507
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
507508
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
509+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
510+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
508511
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
509512
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
510513
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
@@ -551,6 +554,7 @@ fn modifier_to_llvm(
551554
}
552555
}
553556
InlineAsmRegClass::Hexagon(_) => None,
557+
InlineAsmRegClass::Mips(_) => None,
554558
InlineAsmRegClass::Nvptx(_) => None,
555559
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
556560
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
@@ -603,6 +607,8 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
603607
cx.type_vector(cx.type_i64(), 2)
604608
}
605609
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
610+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
611+
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
606612
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
607613
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
608614
InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
@@ -700,6 +706,12 @@ fn llvm_fixup_input(
700706
value
701707
}
702708
}
709+
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
710+
// MIPS only supports register-length arithmetics.
711+
Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
712+
Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
713+
_ => value,
714+
},
703715
_ => value,
704716
}
705717
}
@@ -768,6 +780,13 @@ fn llvm_fixup_output(
768780
value
769781
}
770782
}
783+
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
784+
// MIPS only supports register-length arithmetics.
785+
Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
786+
Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
787+
Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
788+
_ => value,
789+
},
771790
_ => value,
772791
}
773792
}
@@ -831,6 +850,12 @@ fn llvm_fixup_output_type(
831850
layout.llvm_type(cx)
832851
}
833852
}
853+
(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
854+
// MIPS only supports register-length arithmetics.
855+
Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
856+
Primitive::F32 => cx.type_i32(),
857+
_ => layout.llvm_type(cx),
858+
},
834859
_ => layout.llvm_type(cx),
835860
}
836861
}

‎compiler/rustc_lint/src/lib.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -305,6 +305,7 @@ fn register_builtins(store: &mut LintStore, no_interleave_lints: bool) {
305305
add_lint_group!(
306306
"rustdoc",
307307
BROKEN_INTRA_DOC_LINKS,
308+
PRIVATE_INTRA_DOC_LINKS,
308309
INVALID_CODEBLOCK_ATTRIBUTES,
309310
MISSING_DOC_CODE_EXAMPLES,
310311
PRIVATE_DOC_TESTS

‎compiler/rustc_mir/src/const_eval/fn_queries.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ pub fn is_min_const_fn(tcx: TyCtxt<'_>, def_id: DefId) -> bool {
5050
None => {
5151
if let Some(stab) = tcx.lookup_stability(def_id) {
5252
if stab.level.is_stable() {
53-
tcx.sess.span_err(
53+
tcx.sess.delay_span_bug(
5454
tcx.def_span(def_id),
5555
"stable const functions must have either `rustc_const_stable` or \
5656
`rustc_const_unstable` attribute",

‎compiler/rustc_mir/src/transform/check_consts/validation.rs

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -204,9 +204,6 @@ impl Validator<'mir, 'tcx> {
204204
pub fn check_body(&mut self) {
205205
let ConstCx { tcx, body, def_id, .. } = *self.ccx;
206206

207-
// HACK: This function has side-effects???? Make sure we call it.
208-
let _ = crate::const_eval::is_min_const_fn(tcx, def_id.to_def_id());
209-
210207
// The local type and predicate checks are not free and only relevant for `const fn`s.
211208
if self.const_kind() == hir::ConstContext::ConstFn {
212209
// Prevent const trait methods from being annotated as `stable`.

‎compiler/rustc_passes/src/stability.rs

Lines changed: 31 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -459,6 +459,21 @@ impl<'tcx> MissingStabilityAnnotations<'tcx> {
459459
self.tcx.sess.span_err(span, &format!("{} has missing stability attribute", descr));
460460
}
461461
}
462+
463+
fn check_missing_const_stability(&self, hir_id: HirId, span: Span) {
464+
let stab_map = self.tcx.stability();
465+
let stab = stab_map.local_stability(hir_id);
466+
if stab.map_or(false, |stab| stab.level.is_stable()) {
467+
let const_stab = stab_map.local_const_stability(hir_id);
468+
if const_stab.is_none() {
469+
self.tcx.sess.span_err(
470+
span,
471+
"`#[stable]` const functions must also be either \
472+
`#[rustc_const_stable]` or `#[rustc_const_unstable]`",
473+
);
474+
}
475+
}
476+
}
462477
}
463478

464479
impl<'tcx> Visitor<'tcx> for MissingStabilityAnnotations<'tcx> {
@@ -469,14 +484,23 @@ impl<'tcx> Visitor<'tcx> for MissingStabilityAnnotations<'tcx> {
469484
}
470485

471486
fn visit_item(&mut self, i: &'tcx Item<'tcx>) {
472-
match i.kind {
473-
// Inherent impls and foreign modules serve only as containers for other items,
474-
// they don't have their own stability. They still can be annotated as unstable
475-
// and propagate this unstability to children, but this annotation is completely
476-
// optional. They inherit stability from their parents when unannotated.
477-
hir::ItemKind::Impl { of_trait: None, .. } | hir::ItemKind::ForeignMod(..) => {}
487+
// Inherent impls and foreign modules serve only as containers for other items,
488+
// they don't have their own stability. They still can be annotated as unstable
489+
// and propagate this unstability to children, but this annotation is completely
490+
// optional. They inherit stability from their parents when unannotated.
491+
if !matches!(
492+
i.kind,
493+
hir::ItemKind::Impl { of_trait: None, .. } | hir::ItemKind::ForeignMod(..)
494+
) {
495+
self.check_missing_stability(i.hir_id, i.span);
496+
}
478497

479-
_ => self.check_missing_stability(i.hir_id, i.span),
498+
// Ensure `const fn` that are `stable` have one of `rustc_const_unstable` or
499+
// `rustc_const_stable`.
500+
if self.tcx.features().staged_api
501+
&& matches!(&i.kind, hir::ItemKind::Fn(sig, ..) if sig.header.is_const())
502+
{
503+
self.check_missing_const_stability(i.hir_id, i.span);
480504
}
481505

482506
intravisit::walk_item(self, i)

‎compiler/rustc_session/src/lint/builtin.rs

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1826,6 +1826,17 @@ declare_lint! {
18261826
"failures in resolving intra-doc link targets"
18271827
}
18281828

1829+
declare_lint! {
1830+
/// This is a subset of `broken_intra_doc_links` that warns when linking from
1831+
/// a public item to a private one. This is a `rustdoc` only lint, see the
1832+
/// documentation in the [rustdoc book].
1833+
///
1834+
/// [rustdoc book]: ../../../rustdoc/lints.html#private_intra_doc_links
1835+
pub PRIVATE_INTRA_DOC_LINKS,
1836+
Warn,
1837+
"linking from a public item to a private one"
1838+
}
1839+
18291840
declare_lint! {
18301841
/// The `invalid_codeblock_attributes` lint detects code block attributes
18311842
/// in documentation examples that have potentially mis-typed values. This

‎compiler/rustc_session/src/session.rs

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1103,9 +1103,6 @@ impl Session {
11031103
self.used_attrs.lock().is_marked(attr)
11041104
}
11051105

1106-
/// Returns `true` if the attribute's path matches the argument. If it matches, then the
1107-
/// attribute is marked as used.
1108-
11091106
/// Returns `true` if the attribute's path matches the argument. If it
11101107
/// matches, then the attribute is marked as used.
11111108
///

‎compiler/rustc_span/src/hygiene.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -702,7 +702,7 @@ pub struct ExpnData {
702702
/// The `DefId` of the macro being invoked,
703703
/// if this `ExpnData` corresponds to a macro invocation
704704
pub macro_def_id: Option<DefId>,
705-
/// The crate that originally created this `ExpnData. During
705+
/// The crate that originally created this `ExpnData`. During
706706
/// metadata serialization, we only encode `ExpnData`s that were
707707
/// created locally - when our serialized metadata is decoded,
708708
/// foreign `ExpnId`s will have their `ExpnData` looked up
@@ -759,7 +759,7 @@ impl ExpnData {
759759

760760
#[inline]
761761
pub fn is_root(&self) -> bool {
762-
if let ExpnKind::Root = self.kind { true } else { false }
762+
matches!(self.kind, ExpnKind::Root)
763763
}
764764
}
765765

‎compiler/rustc_target/src/asm/mips.rs

Lines changed: 132 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,132 @@
1+
use super::{InlineAsmArch, InlineAsmType};
2+
use rustc_macros::HashStable_Generic;
3+
use std::fmt;
4+
5+
def_reg_class! {
6+
Mips MipsInlineAsmRegClass {
7+
reg,
8+
freg,
9+
}
10+
}
11+
12+
impl MipsInlineAsmRegClass {
13+
pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
14+
&[]
15+
}
16+
17+
pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
18+
None
19+
}
20+
21+
pub fn suggest_modifier(
22+
self,
23+
_arch: InlineAsmArch,
24+
_ty: InlineAsmType,
25+
) -> Option<(char, &'static str)> {
26+
None
27+
}
28+
29+
pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
30+
None
31+
}
32+
33+
pub fn supported_types(
34+
self,
35+
_arch: InlineAsmArch,
36+
) -> &'static [(InlineAsmType, Option<&'static str>)] {
37+
match self {
38+
Self::reg => types! { _: I8, I16, I32, F32; },
39+
Self::freg => types! { _: F32; },
40+
}
41+
}
42+
}
43+
44+
// The reserved registers are somewhat taken from <https://git.io/JUR1k#L150>.
45+
def_regs! {
46+
Mips MipsInlineAsmReg MipsInlineAsmRegClass {
47+
v0: reg = ["$2", "$v0"],
48+
v1: reg = ["$3", "$v1"],
49+
a0: reg = ["$4", "$a0"],
50+
a1: reg = ["$5", "$a1"],
51+
a2: reg = ["$6", "$a2"],
52+
a3: reg = ["$7", "$a3"],
53+
// FIXME: Reserve $t0, $t1 if in mips16 mode.
54+
t0: reg = ["$8", "$t0"],
55+
t1: reg = ["$9", "$t1"],
56+
t2: reg = ["$10", "$t2"],
57+
t3: reg = ["$11", "$t3"],
58+
t4: reg = ["$12", "$t4"],
59+
t5: reg = ["$13", "$t5"],
60+
t6: reg = ["$14", "$t6"],
61+
t7: reg = ["$15", "$t7"],
62+
s0: reg = ["$16", "$s0"],
63+
s1: reg = ["$17", "$s1"],
64+
s2: reg = ["$18", "$s2"],
65+
s3: reg = ["$19", "$s3"],
66+
s4: reg = ["$20", "$s4"],
67+
s5: reg = ["$21", "$s5"],
68+
s6: reg = ["$22", "$s6"],
69+
s7: reg = ["$23", "$s7"],
70+
t8: reg = ["$24", "$t8"],
71+
t9: reg = ["$25", "$t9"],
72+
f0: freg = ["$f0"],
73+
f1: freg = ["$f1"],
74+
f2: freg = ["$f2"],
75+
f3: freg = ["$f3"],
76+
f4: freg = ["$f4"],
77+
f5: freg = ["$f5"],
78+
f6: freg = ["$f6"],
79+
f7: freg = ["$f7"],
80+
f8: freg = ["$f8"],
81+
f9: freg = ["$f9"],
82+
f10: freg = ["$f10"],
83+
f11: freg = ["$f11"],
84+
f12: freg = ["$f12"],
85+
f13: freg = ["$f13"],
86+
f14: freg = ["$f14"],
87+
f15: freg = ["$f15"],
88+
f16: freg = ["$f16"],
89+
f17: freg = ["$f17"],
90+
f18: freg = ["$f18"],
91+
f19: freg = ["$f19"],
92+
f20: freg = ["$f20"],
93+
f21: freg = ["$f21"],
94+
f22: freg = ["$f22"],
95+
f23: freg = ["$f23"],
96+
f24: freg = ["$f24"],
97+
f25: freg = ["$f25"],
98+
f26: freg = ["$f26"],
99+
f27: freg = ["$f27"],
100+
f28: freg = ["$f28"],
101+
f29: freg = ["$f29"],
102+
f30: freg = ["$f30"],
103+
f31: freg = ["$f31"],
104+
#error = ["$0", "$zero"] =>
105+
"constant zero cannot be used as an operand for inline asm",
106+
#error = ["$1", "$at"] =>
107+
"reserved for assembler (Assembler Temp)",
108+
#error = ["$26", "$k0"] =>
109+
"OS-reserved register cannot be used as an operand for inline asm",
110+
#error = ["$27", "$k1"] =>
111+
"OS-reserved register cannot be used as an operand for inline asm",
112+
#error = ["$28", "$gp"] =>
113+
"the global pointer cannot be used as an operand for inline asm",
114+
#error = ["$29", "$sp"] =>
115+
"the stack pointer cannot be used as an operand for inline asm",
116+
#error = ["$30", "$s8", "$fp"] =>
117+
"the frame pointer cannot be used as an operand for inline asm",
118+
#error = ["$31", "$ra"] =>
119+
"the return address register cannot be used as an operand for inline asm",
120+
}
121+
}
122+
123+
impl MipsInlineAsmReg {
124+
pub fn emit(
125+
self,
126+
out: &mut dyn fmt::Write,
127+
_arch: InlineAsmArch,
128+
_modifier: Option<char>,
129+
) -> fmt::Result {
130+
out.write_str(self.name())
131+
}
132+
}

‎compiler/rustc_target/src/asm/mod.rs

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -152,13 +152,15 @@ macro_rules! types {
152152
mod aarch64;
153153
mod arm;
154154
mod hexagon;
155+
mod mips;
155156
mod nvptx;
156157
mod riscv;
157158
mod x86;
158159

159160
pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
160161
pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
161162
pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
163+
pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
162164
pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
163165
pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
164166
pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
@@ -173,6 +175,7 @@ pub enum InlineAsmArch {
173175
RiscV64,
174176
Nvptx64,
175177
Hexagon,
178+
Mips,
176179
}
177180

178181
impl FromStr for InlineAsmArch {
@@ -188,6 +191,7 @@ impl FromStr for InlineAsmArch {
188191
"riscv64" => Ok(Self::RiscV64),
189192
"nvptx64" => Ok(Self::Nvptx64),
190193
"hexagon" => Ok(Self::Hexagon),
194+
"mips" => Ok(Self::Mips),
191195
_ => Err(()),
192196
}
193197
}
@@ -201,6 +205,7 @@ pub enum InlineAsmReg {
201205
RiscV(RiscVInlineAsmReg),
202206
Nvptx(NvptxInlineAsmReg),
203207
Hexagon(HexagonInlineAsmReg),
208+
Mips(MipsInlineAsmReg),
204209
}
205210

206211
impl InlineAsmReg {
@@ -211,6 +216,7 @@ impl InlineAsmReg {
211216
Self::AArch64(r) => r.name(),
212217
Self::RiscV(r) => r.name(),
213218
Self::Hexagon(r) => r.name(),
219+
Self::Mips(r) => r.name(),
214220
}
215221
}
216222

@@ -221,6 +227,7 @@ impl InlineAsmReg {
221227
Self::AArch64(r) => InlineAsmRegClass::AArch64(r.reg_class()),
222228
Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
223229
Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
230+
Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
224231
}
225232
}
226233

@@ -252,6 +259,9 @@ impl InlineAsmReg {
252259
InlineAsmArch::Hexagon => {
253260
Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
254261
}
262+
InlineAsmArch::Mips => {
263+
Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
264+
}
255265
})
256266
}
257267

@@ -269,6 +279,7 @@ impl InlineAsmReg {
269279
Self::AArch64(r) => r.emit(out, arch, modifier),
270280
Self::RiscV(r) => r.emit(out, arch, modifier),
271281
Self::Hexagon(r) => r.emit(out, arch, modifier),
282+
Self::Mips(r) => r.emit(out, arch, modifier),
272283
}
273284
}
274285

@@ -279,6 +290,7 @@ impl InlineAsmReg {
279290
Self::AArch64(_) => cb(self),
280291
Self::RiscV(_) => cb(self),
281292
Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
293+
Self::Mips(_) => cb(self),
282294
}
283295
}
284296
}
@@ -291,6 +303,7 @@ pub enum InlineAsmRegClass {
291303
RiscV(RiscVInlineAsmRegClass),
292304
Nvptx(NvptxInlineAsmRegClass),
293305
Hexagon(HexagonInlineAsmRegClass),
306+
Mips(MipsInlineAsmRegClass),
294307
}
295308

296309
impl InlineAsmRegClass {
@@ -302,6 +315,7 @@ impl InlineAsmRegClass {
302315
Self::RiscV(r) => r.name(),
303316
Self::Nvptx(r) => r.name(),
304317
Self::Hexagon(r) => r.name(),
318+
Self::Mips(r) => r.name(),
305319
}
306320
}
307321

@@ -316,6 +330,7 @@ impl InlineAsmRegClass {
316330
Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
317331
Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
318332
Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
333+
Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
319334
}
320335
}
321336

@@ -337,6 +352,7 @@ impl InlineAsmRegClass {
337352
Self::RiscV(r) => r.suggest_modifier(arch, ty),
338353
Self::Nvptx(r) => r.suggest_modifier(arch, ty),
339354
Self::Hexagon(r) => r.suggest_modifier(arch, ty),
355+
Self::Mips(r) => r.suggest_modifier(arch, ty),
340356
}
341357
}
342358

@@ -354,6 +370,7 @@ impl InlineAsmRegClass {
354370
Self::RiscV(r) => r.default_modifier(arch),
355371
Self::Nvptx(r) => r.default_modifier(arch),
356372
Self::Hexagon(r) => r.default_modifier(arch),
373+
Self::Mips(r) => r.default_modifier(arch),
357374
}
358375
}
359376

@@ -370,6 +387,7 @@ impl InlineAsmRegClass {
370387
Self::RiscV(r) => r.supported_types(arch),
371388
Self::Nvptx(r) => r.supported_types(arch),
372389
Self::Hexagon(r) => r.supported_types(arch),
390+
Self::Mips(r) => r.supported_types(arch),
373391
}
374392
}
375393

@@ -391,6 +409,7 @@ impl InlineAsmRegClass {
391409
InlineAsmArch::Hexagon => {
392410
Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
393411
}
412+
InlineAsmArch::Mips => Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?),
394413
})
395414
})
396415
}
@@ -405,6 +424,7 @@ impl InlineAsmRegClass {
405424
Self::RiscV(r) => r.valid_modifiers(arch),
406425
Self::Nvptx(r) => r.valid_modifiers(arch),
407426
Self::Hexagon(r) => r.valid_modifiers(arch),
427+
Self::Mips(r) => r.valid_modifiers(arch),
408428
}
409429
}
410430
}
@@ -545,5 +565,10 @@ pub fn allocatable_registers(
545565
hexagon::fill_reg_map(arch, has_feature, target, &mut map);
546566
map
547567
}
568+
InlineAsmArch::Mips => {
569+
let mut map = mips::regclass_map();
570+
mips::fill_reg_map(arch, has_feature, target, &mut map);
571+
map
572+
}
548573
}
549574
}

‎src/bootstrap/defaults/README.md

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,8 @@ These defaults are intended to be a good starting point for working with x.py,
44
with the understanding that no one set of defaults make sense for everyone.
55

66
They are still experimental, and we'd appreciate your help improving them!
7-
If you use a setting that's not in these defaults that you think others would benefit from, please [file an issue] or make a PR with the changes.
7+
If you use a setting that's not in these defaults that you think
8+
others would benefit from, please [file an issue] or make a PR with the changes.
89
Similarly, if one of these defaults doesn't match what you use personally,
910
please open an issue to get it changed.
1011

‎src/doc/rustdoc/src/lints.md

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,46 @@ help: to link to the function, add parentheses
6262
6363
```
6464

65+
## private_intra_doc_links
66+
67+
This lint **warns by default**. This lint detects when [intra-doc links] from public to private items.
68+
For example:
69+
70+
```rust
71+
/// [private]
72+
pub fn public() {}
73+
fn private() {}
74+
```
75+
76+
This gives a warning that the link will be broken when it appears in your documentation:
77+
78+
```text
79+
warning: public documentation for `public` links to private item `private`
80+
--> priv.rs:1:6
81+
|
82+
1 | /// [private]
83+
| ^^^^^^^ this item is private
84+
|
85+
= note: `#[warn(private_intra_doc_links)]` on by default
86+
= note: this link will resolve properly if you pass `--document-private-items`
87+
```
88+
89+
Note that this has different behavior depending on whether you pass `--document-private-items` or not!
90+
If you document private items, then it will still generate a link, despite the warning:
91+
92+
```text
93+
warning: public documentation for `public` links to private item `private`
94+
--> priv.rs:1:6
95+
|
96+
1 | /// [private]
97+
| ^^^^^^^ this item is private
98+
|
99+
= note: `#[warn(private_intra_doc_links)]` on by default
100+
= note: this link resolves only because you passed `--document-private-items`, but will break without
101+
```
102+
103+
[intra-doc links]: linking-to-items-by-name.html
104+
65105
## missing_docs
66106

67107
This lint is **allowed by default**. It detects items missing documentation.

‎src/doc/unstable-book/src/library-features/asm.md

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ Inline assembly is currently supported on the following architectures:
2727
- RISC-V
2828
- NVPTX
2929
- Hexagon
30+
- MIPS32
3031

3132
## Basic usage
3233

@@ -512,6 +513,8 @@ Here is the list of currently supported register classes:
512513
| ARM | `qreg` | `q[0-15]` | `w` |
513514
| ARM | `qreg_low8` | `q[0-7]` | `t` |
514515
| ARM | `qreg_low4` | `q[0-3]` | `x` |
516+
| MIPS32 | `reg` | `$[2-25]` | `r` |
517+
| MIPS32 | `freg` | `$f[0-31]` | `f` |
515518
| NVPTX | `reg16` | None\* | `h` |
516519
| NVPTX | `reg32` | None\* | `r` |
517520
| NVPTX | `reg64` | None\* | `l` |
@@ -547,6 +550,8 @@ Each register class has constraints on which value types they can be used with.
547550
| ARM | `sreg` | `vfp2` | `i32`, `f32` |
548551
| ARM | `dreg` | `vfp2` | `i64`, `f64`, `i8x8`, `i16x4`, `i32x2`, `i64x1`, `f32x2` |
549552
| ARM | `qreg` | `neon` | `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4` |
553+
| MIPS32 | `reg` | None | `i8`, `i16`, `i32`, `f32` |
554+
| MIPS32 | `freg` | None | `f32` |
550555
| NVPTX | `reg16` | None | `i8`, `i16` |
551556
| NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
552557
| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
@@ -595,6 +600,7 @@ Some registers have multiple names. These are all treated by the compiler as ide
595600
| ARM | `r13` | `sp` |
596601
| ARM | `r14` | `lr` |
597602
| ARM | `r15` | `pc` |
603+
| MIPS32 | `$[2-25]` | Please [see the Wikipedia page][mips-regs] |
598604
| RISC-V | `x0` | `zero` |
599605
| RISC-V | `x1` | `ra` |
600606
| RISC-V | `x2` | `sp` |
@@ -615,12 +621,14 @@ Some registers have multiple names. These are all treated by the compiler as ide
615621
| Hexagon | `r30` | `fr` |
616622
| Hexagon | `r31` | `lr` |
617623

624+
[mips-regs]: https://en.wikibooks.org/wiki/MIPS_Assembly/Register_File#Registers
625+
618626
Some registers cannot be used for input or output operands:
619627

620628
| Architecture | Unsupported register | Reason |
621629
| ------------ | -------------------- | ------ |
622630
| All | `sp` | The stack pointer must be restored to its original value at the end of an asm code block. |
623-
| All | `bp` (x86), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon) | The frame pointer cannot be used as an input or output. |
631+
| All | `bp` (x86), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon), `$fp` (MIPS) | The frame pointer cannot be used as an input or output. |
624632
| ARM | `r7` or `r11` | On ARM the frame pointer can be either `r7` or `r11` depending on the target. The frame pointer cannot be used as an input or output. |
625633
| ARM | `r6` | `r6` is used internally by LLVM as a base pointer and therefore cannot be used as an input or output. |
626634
| x86 | `k0` | This is a constant zero register which can't be modified. |
@@ -629,6 +637,11 @@ Some registers cannot be used for input or output operands:
629637
| x86 | `st([0-7])` | x87 registers are not currently supported (but may be in the future). |
630638
| AArch64 | `xzr` | This is a constant zero register which can't be modified. |
631639
| ARM | `pc` | This is the program counter, not a real register. |
640+
| MIPS32 | `$0` or `$zero` | This is a constant zero register which can't be modified. |
641+
| MIPS32 | `$1` or `$at` | Reserved for assembler. |
642+
| MIPS32 | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
643+
| MIPS32 | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
644+
| MIPS32 | `$ra` | Return address cannot be used as inputs or outputs. |
632645
| RISC-V | `x0` | This is a constant zero register which can't be modified. |
633646
| RISC-V | `gp`, `tp` | These registers are reserved and cannot be used as inputs or outputs. |
634647
| Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
@@ -676,6 +689,8 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
676689
| ARM | `dreg` | None | `d0` | `P` |
677690
| ARM | `qreg` | None | `q0` | `q` |
678691
| ARM | `qreg` | `e` / `f` | `d0` / `d1` | `e` / `f` |
692+
| MIPS32 | `reg` | None | `$2` | None |
693+
| MIPS32 | `freg` | None | `$f0` | None |
679694
| NVPTX | `reg16` | None | `rs0` | None |
680695
| NVPTX | `reg32` | None | `r0` | None |
681696
| NVPTX | `reg64` | None | `rd0` | None |

‎src/librustdoc/passes/collect_intra_doc_links.rs

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,10 @@ use rustc_hir::def::{
1111
use rustc_hir::def_id::DefId;
1212
use rustc_middle::ty;
1313
use rustc_resolve::ParentScope;
14-
use rustc_session::lint;
14+
use rustc_session::lint::{
15+
builtin::{BROKEN_INTRA_DOC_LINKS, PRIVATE_INTRA_DOC_LINKS},
16+
Lint,
17+
};
1518
use rustc_span::hygiene::MacroKind;
1619
use rustc_span::symbol::Ident;
1720
use rustc_span::symbol::Symbol;
@@ -988,7 +991,7 @@ impl LinkCollector<'_, '_> {
988991
let report_mismatch = |specified: Disambiguator, resolved: Disambiguator| {
989992
// The resolved item did not match the disambiguator; give a better error than 'not found'
990993
let msg = format!("incompatible link kind for `{}`", path_str);
991-
report_diagnostic(cx, &msg, &item, dox, &link_range, |diag, sp| {
994+
let callback = |diag: &mut DiagnosticBuilder<'_>, sp| {
992995
let note = format!(
993996
"this link resolved to {} {}, which is not {} {}",
994997
resolved.article(),
@@ -998,7 +1001,8 @@ impl LinkCollector<'_, '_> {
9981001
);
9991002
diag.note(&note);
10001003
suggest_disambiguator(resolved, diag, path_str, dox, sp, &link_range);
1001-
});
1004+
};
1005+
report_diagnostic(cx, BROKEN_INTRA_DOC_LINKS, &msg, &item, dox, &link_range, callback);
10021006
};
10031007
if let Res::PrimTy(..) = res {
10041008
match disambiguator {
@@ -1055,7 +1059,6 @@ impl LinkCollector<'_, '_> {
10551059
&& !self.cx.tcx.privacy_access_levels(LOCAL_CRATE).is_exported(hir_dst)
10561060
{
10571061
privacy_error(cx, &item, &path_str, dox, link_range);
1058-
return;
10591062
}
10601063
}
10611064
let id = register_res(cx, res);
@@ -1417,6 +1420,7 @@ impl Suggestion {
14171420
/// to it.
14181421
fn report_diagnostic(
14191422
cx: &DocContext<'_>,
1423+
lint: &'static Lint,
14201424
msg: &str,
14211425
item: &Item,
14221426
dox: &str,
@@ -1435,7 +1439,7 @@ fn report_diagnostic(
14351439
let attrs = &item.attrs;
14361440
let sp = span_of_attrs(attrs).unwrap_or(item.source.span());
14371441

1438-
cx.tcx.struct_span_lint_hir(lint::builtin::BROKEN_INTRA_DOC_LINKS, hir_id, sp, |lint| {
1442+
cx.tcx.struct_span_lint_hir(lint, hir_id, sp, |lint| {
14391443
let mut diag = lint.build(msg);
14401444

14411445
let span = link_range
@@ -1482,6 +1486,7 @@ fn resolution_failure(
14821486
) {
14831487
report_diagnostic(
14841488
collector.cx,
1489+
BROKEN_INTRA_DOC_LINKS,
14851490
&format!("unresolved link to `{}`", path_str),
14861491
item,
14871492
dox,
@@ -1695,7 +1700,7 @@ fn anchor_failure(
16951700
),
16961701
};
16971702

1698-
report_diagnostic(cx, &msg, item, dox, &link_range, |diag, sp| {
1703+
report_diagnostic(cx, BROKEN_INTRA_DOC_LINKS, &msg, item, dox, &link_range, |diag, sp| {
16991704
if let Some(sp) = sp {
17001705
diag.span_label(sp, "contains invalid anchor");
17011706
}
@@ -1734,7 +1739,7 @@ fn ambiguity_error(
17341739
}
17351740
}
17361741

1737-
report_diagnostic(cx, &msg, item, dox, &link_range, |diag, sp| {
1742+
report_diagnostic(cx, BROKEN_INTRA_DOC_LINKS, &msg, item, dox, &link_range, |diag, sp| {
17381743
if let Some(sp) = sp {
17391744
diag.span_label(sp, "ambiguous link");
17401745
} else {
@@ -1784,7 +1789,7 @@ fn privacy_error(
17841789
let msg =
17851790
format!("public documentation for `{}` links to private item `{}`", item_name, path_str);
17861791

1787-
report_diagnostic(cx, &msg, item, dox, &link_range, |diag, sp| {
1792+
report_diagnostic(cx, PRIVATE_INTRA_DOC_LINKS, &msg, item, dox, &link_range, |diag, sp| {
17881793
if let Some(sp) = sp {
17891794
diag.span_label(sp, "this item is private");
17901795
}

‎src/test/assembly/asm/mips-types.rs

Lines changed: 191 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,191 @@
1+
// no-system-llvm
2+
// assembly-output: emit-asm
3+
// compile-flags: --target mips-unknown-linux-gnu
4+
// needs-llvm-components: mips
5+
6+
#![feature(no_core, lang_items, rustc_attrs, repr_simd)]
7+
#![crate_type = "rlib"]
8+
#![no_core]
9+
#![allow(asm_sub_register, non_camel_case_types)]
10+
11+
#[rustc_builtin_macro]
12+
macro_rules! asm {
13+
() => {};
14+
}
15+
#[rustc_builtin_macro]
16+
macro_rules! concat {
17+
() => {};
18+
}
19+
#[rustc_builtin_macro]
20+
macro_rules! stringify {
21+
() => {};
22+
}
23+
24+
#[lang = "sized"]
25+
trait Sized {}
26+
#[lang = "copy"]
27+
trait Copy {}
28+
29+
type ptr = *const i32;
30+
31+
impl Copy for i8 {}
32+
impl Copy for u8 {}
33+
impl Copy for i16 {}
34+
impl Copy for i32 {}
35+
impl Copy for f32 {}
36+
impl Copy for ptr {}
37+
extern "C" {
38+
fn extern_func();
39+
static extern_static: u8;
40+
}
41+
42+
// Hack to avoid function merging
43+
extern "Rust" {
44+
fn dont_merge(s: &str);
45+
}
46+
47+
macro_rules! check { ($func:ident, $ty:ty, $class:ident) => {
48+
#[no_mangle]
49+
pub unsafe fn $func(x: $ty) -> $ty {
50+
dont_merge(stringify!($func));
51+
52+
let y;
53+
asm!("move {}, {}", out($class) y, in($class) x);
54+
y
55+
}
56+
};}
57+
58+
macro_rules! check_reg { ($func:ident, $ty:ty, $reg:tt) => {
59+
#[no_mangle]
60+
pub unsafe fn $func(x: $ty) -> $ty {
61+
dont_merge(stringify!($func));
62+
63+
let y;
64+
asm!(concat!("move ", $reg, ", ", $reg), lateout($reg) y, in($reg) x);
65+
y
66+
}
67+
};}
68+
69+
// CHECK-LABEL: sym_static:
70+
// CHECK: #APP
71+
// CHECK: lw $3, %got(extern_static)
72+
// CHECK: #NO_APP
73+
#[no_mangle]
74+
pub unsafe fn sym_static() {
75+
dont_merge(stringify!($func));
76+
77+
asm!("la $v1, {}", sym extern_static);
78+
}
79+
80+
// CHECK-LABEL: sym_fn:
81+
// CHECK: #APP
82+
// CHECK: lw $3, %got(extern_func)
83+
// CHECK: #NO_APP
84+
#[no_mangle]
85+
pub unsafe fn sym_fn() {
86+
dont_merge(stringify!($func));
87+
88+
asm!("la $v1, {}", sym extern_func);
89+
}
90+
91+
// CHECK-LABEL: reg_f32:
92+
// CHECK: #APP
93+
// CHECK: mov.s $f{{[0-9]+}}, $f{{[0-9]+}}
94+
// CHECK: #NO_APP
95+
#[no_mangle]
96+
pub unsafe fn reg_f32(x: f32) -> f32 {
97+
dont_merge("reg_f32");
98+
let y;
99+
asm!("mov.s {}, {}", out(freg) y, in(freg) x);
100+
y
101+
}
102+
103+
// CHECK-LABEL: f0_f32:
104+
// CHECK: #APP
105+
// CHECK: mov.s $f0, $f0
106+
// CHECK: #NO_APP
107+
#[no_mangle]
108+
pub unsafe fn f0_f32(x: f32) -> f32 {
109+
dont_merge("f0_f32");
110+
let y;
111+
asm!("mov.s $f0, $f0", lateout("$f0") y, in("$f0") x);
112+
y
113+
}
114+
115+
// CHECK-LABEL: reg_ptr:
116+
// CHECK: #APP
117+
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
118+
// CHECK: #NO_APP
119+
check!(reg_ptr, ptr, reg);
120+
121+
// CHECK-LABEL: reg_i32:
122+
// CHECK: #APP
123+
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
124+
// CHECK: #NO_APP
125+
check!(reg_i32, i32, reg);
126+
127+
// CHECK-LABEL: reg_f32_soft:
128+
// CHECK: #APP
129+
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
130+
// CHECK: #NO_APP
131+
check!(reg_f32_soft, f32, reg);
132+
133+
// CHECK-LABEL: reg_i8:
134+
// CHECK: #APP
135+
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
136+
// CHECK: #NO_APP
137+
check!(reg_i8, i8, reg);
138+
139+
// CHECK-LABEL: reg_u8:
140+
// CHECK: #APP
141+
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
142+
// CHECK: #NO_APP
143+
check!(reg_u8, u8, reg);
144+
145+
// CHECK-LABEL: reg_i16:
146+
// CHECK: #APP
147+
// CHECK: move ${{[0-9]+}}, ${{[0-9]+}}
148+
// CHECK: #NO_APP
149+
check!(reg_i16, i16, reg);
150+
151+
// CHECK-LABEL: t0_ptr:
152+
// CHECK: #APP
153+
// CHECK: move $8, $8
154+
// CHECK: #NO_APP
155+
check_reg!(t0_ptr, ptr, "$t0");
156+
157+
// CHECK-LABEL: t0_i32:
158+
// CHECK: #APP
159+
// CHECK: move $8, $8
160+
// CHECK: #NO_APP
161+
check_reg!(t0_i32, i32, "$t0");
162+
163+
// CHECK-LABEL: t0_f32:
164+
// CHECK: #APP
165+
// CHECK: move $8, $8
166+
// CHECK: #NO_APP
167+
check_reg!(t0_f32, f32, "$t0");
168+
169+
// CHECK-LABEL: t0_i8:
170+
// CHECK: #APP
171+
// CHECK: move $8, $8
172+
// CHECK: #NO_APP
173+
check_reg!(t0_i8, i8, "$t0");
174+
175+
// CHECK-LABEL: t0_u8:
176+
// CHECK: #APP
177+
// CHECK: move $8, $8
178+
// CHECK: #NO_APP
179+
check_reg!(t0_u8, u8, "$t0");
180+
181+
// CHECK-LABEL: t0_i16:
182+
// CHECK: #APP
183+
// CHECK: move $8, $8
184+
// CHECK: #NO_APP
185+
check_reg!(t0_i16, i16, "$t0");
186+
187+
// CHECK-LABEL: r8_i16:
188+
// CHECK: #APP
189+
// CHECK: move $8, $8
190+
// CHECK: #NO_APP
191+
check_reg!(r8_i16, i16, "$8");

‎src/test/rustdoc-ui/intra-links-private.private.stderr

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ warning: public documentation for `DocMe` links to private item `DontDocMe`
44
LL | /// docs [DontDocMe]
55
| ^^^^^^^^^ this item is private
66
|
7-
= note: `#[warn(broken_intra_doc_links)]` on by default
7+
= note: `#[warn(private_intra_doc_links)]` on by default
88
= note: this link resolves only because you passed `--document-private-items`, but will break without
99

1010
warning: 1 warning emitted

‎src/test/rustdoc-ui/intra-links-private.public.stderr

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ warning: public documentation for `DocMe` links to private item `DontDocMe`
44
LL | /// docs [DontDocMe]
55
| ^^^^^^^^^ this item is private
66
|
7-
= note: `#[warn(broken_intra_doc_links)]` on by default
7+
= note: `#[warn(private_intra_doc_links)]` on by default
88
= note: this link will resolve properly if you pass `--document-private-items`
99

1010
warning: 1 warning emitted

‎src/test/rustdoc-ui/issue-74134.private.stderr

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ warning: public documentation for `public_item` links to private item `PrivateTy
44
LL | /// [`PrivateType`]
55
| ^^^^^^^^^^^^^ this item is private
66
|
7-
= note: `#[warn(broken_intra_doc_links)]` on by default
7+
= note: `#[warn(private_intra_doc_links)]` on by default
88
= note: this link resolves only because you passed `--document-private-items`, but will break without
99

1010
warning: 1 warning emitted

‎src/test/rustdoc-ui/issue-74134.public.stderr

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ warning: public documentation for `public_item` links to private item `PrivateTy
44
LL | /// [`PrivateType`]
55
| ^^^^^^^^^^^^^ this item is private
66
|
7-
= note: `#[warn(broken_intra_doc_links)]` on by default
7+
= note: `#[warn(private_intra_doc_links)]` on by default
88
= note: this link will resolve properly if you pass `--document-private-items`
99

1010
warning: 1 warning emitted

‎src/test/rustdoc/intra-doc-link-private.rs

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
#![crate_name = "private"]
2+
// compile-flags: --document-private-items
3+
/// docs [DontDocMe]
4+
// @has private/struct.DocMe.html '//*a[@href="../private/struct.DontDocMe.html"]' 'DontDocMe'
5+
pub struct DocMe;
6+
struct DontDocMe;

‎src/test/ui/stability-attribute/missing-const-stability.rs

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
#![feature(staged_api)]
2+
3+
#![stable(feature = "rust1", since = "1.0.0")]
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5+
#[stable(feature = "foo", since = "1.0.0")]
6+
pub const fn foo() {}
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//~^ ERROR rustc_const_stable
8+
9+
#[unstable(feature = "bar", issue = "none")]
10+
pub const fn bar() {} // ok
11+
12+
fn main() {}

‎src/test/ui/stability-attribute/missing-const-stability.stderr

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
error: `#[stable]` const functions must also be either `#[rustc_const_stable]` or `#[rustc_const_unstable]`
2+
--> $DIR/missing-const-stability.rs:6:1
3+
|
4+
LL | pub const fn foo() {}
5+
| ^^^^^^^^^^^^^^^^^^^^^
6+
7+
error: aborting due to previous error
8+

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