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1 parent d8383b6 commit bdb1898Copy full SHA for bdb1898
src/atomics.md
@@ -71,7 +71,7 @@ cache.
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After all, that's the whole point of the cache, right? If every read from the
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cache had to run back to shared memory to double check that it hadn't changed,
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what would the point be? The end result is that the hardware doesn't guarantee
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-that events that occur in the same order on *one* thread, occur in the same
+that events that occur in some order on *one* thread, occur in the same
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order on *another* thread. To guarantee this, we must issue special instructions
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to the CPU telling it to be a bit less smart.
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