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aykevldylanmckay
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[AVR] Fix miscompilation of zext + add
Code like the following: define i32 @foo(i32 %a, i1 zeroext %b) addrspace(1) { entry: %conv = zext i1 %b to i32 %add = add nsw i32 %conv, %a ret i32 %add } Would compile to the following (incorrect) code: foo: mov r18, r20 clr r19 add r22, r18 adc r23, r19 sbci r24, 0 sbci r25, 0 ret Those sbci instructions are clearly wrong, they should have been adc instructions. This commit improves codegen to use adc instead: foo: mov r18, r20 clr r19 ldi r20, 0 ldi r21, 0 add r22, r18 adc r23, r19 adc r24, r20 adc r25, r21 ret This code is not optimal (it could be just 5 instructions instead of the current 9) but at least it doesn't miscompile. Differential Revision: https://reviews.llvm.org/D78439
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llvm/lib/Target/AVR/AVRInstrInfo.td

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@@ -2047,8 +2047,6 @@ def : Pat<(add i16:$src1, imm:$src2),
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(SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
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def : Pat<(addc i16:$src1, imm:$src2),
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(SUBIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
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def : Pat<(adde i16:$src1, imm:$src2),
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(SBCIWRdK i16:$src1, (imm16_neg_XFORM imm:$src2))>;
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def : Pat<(add i8:$src1, imm:$src2),
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(SUBIRdK i8:$src1, (imm8_neg_XFORM imm:$src2))>;

llvm/test/CodeGen/AVR/add.ll

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@@ -45,6 +45,17 @@ define i16 @add16_reg_imm_subi(i16 %a) {
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ret i16 %result
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}
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define i16 @add16_reg_reg_zext(i16 %a, i1 zeroext %b) {
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; CHECK-LABEL: add16_reg_reg_zext:
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; CHECK: mov r18, r22
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; CHECK: clr r19
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; CHECK: add r24, r18
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; CHECK: adc r25, r19
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%zext = zext i1 %b to i16
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%result = add i16 %a, %zext
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ret i16 %result
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}
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define i32 @add32_reg_reg(i32 %a, i32 %b) {
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; CHECK-LABEL: add32_reg_reg:
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; CHECK: add r22, r18
@@ -65,6 +76,21 @@ define i32 @add32_reg_imm(i32 %a) {
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ret i32 %result
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}
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define i32 @add32_reg_reg_zext(i32 %a, i1 zeroext %b) {
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; CHECK-LABEL: add32_reg_reg_zext:
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; CHECK: mov r18, r20
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; CHECK: clr r19
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; CHECK: ldi r20, 0
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; CHECK: ldi r21, 0
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; CHECK: add r22, r18
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; CHECK: adc r23, r19
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; CHECK: adc r24, r20
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; CHECK: adc r25, r21
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%zext = zext i1 %b to i32
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%result = add i32 %a, %zext
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ret i32 %result
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}
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define i64 @add64_reg_reg(i64 %a, i64 %b) {
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; CHECK-LABEL: add64_reg_reg:
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; CHECK: add r18, r10
@@ -91,3 +117,22 @@ define i64 @add64_reg_imm(i64 %a) {
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%result = add i64 %a, 5
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ret i64 %result
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}
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define i64 @add64_reg_reg_zext(i64 %a, i1 zeroext %b) {
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; CHECK-LABEL: add64_reg_reg_zext:
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; CHECK: mov r30, r16
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; CHECK: clr r31
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; CHECK: ldi r26, 0
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; CHECK: ldi r27, 0
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; CHECK: add r18, r30
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; CHECK: adc r19, r31
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; CHECK: adc r20, r26
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; CHECK: adc r21, r27
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; CHECK: adc r22, r26
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; CHECK: adc r23, r27
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; CHECK: adc r24, r26
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; CHECK: adc r25, r27
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%zext = zext i1 %b to i64
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%result = add i64 %a, %zext
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ret i64 %result
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}

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