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fix codegen difference
1 parent 99851c4 commit dd025c3

7 files changed

+88
-34
lines changed

‎library/core/src/num/int_macros.rs

+2-4
Original file line numberDiff line numberDiff line change
@@ -785,8 +785,7 @@ macro_rules! int_impl {
785785
// SAFETY: the caller must uphold the safety contract for
786786
// `unchecked_shl`.
787787
// Any legal shift amount is losslessly representable in the self type.
788-
// FIXME(const-hack) replace with `.try_into().ok().unwrap_unchecked()`.
789-
unsafe { intrinsics::unchecked_shl(self, rhs as _) }
788+
unsafe { intrinsics::unchecked_shl(self, conv_rhs_for_unchecked_shift!($SelfT, rhs)) }
790789
}
791790

792791
/// Checked shift right. Computes `self >> rhs`, returning `None` if `rhs` is
@@ -834,8 +833,7 @@ macro_rules! int_impl {
834833
// SAFETY: the caller must uphold the safety contract for
835834
// `unchecked_shr`.
836835
// Any legal shift amount is losslessly representable in the self type.
837-
// FIXME(const-hack) replace with `.try_into().ok().unwrap_unchecked()`.
838-
unsafe { intrinsics::unchecked_shr(self, rhs as _) }
836+
unsafe { intrinsics::unchecked_shr(self, conv_rhs_for_unchecked_shift!($SelfT, rhs)) }
839837
}
840838

841839
/// Checked absolute value. Computes `self.abs()`, returning `None` if

‎library/core/src/num/mod.rs

+18
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
#![stable(feature = "rust1", since = "1.0.0")]
44

55
use crate::ascii;
6+
use crate::convert::TryInto;
67
use crate::intrinsics;
78
use crate::mem;
89
use crate::ops::{Add, Mul, Sub};
@@ -224,6 +225,23 @@ macro_rules! widening_impl {
224225
};
225226
}
226227

228+
macro_rules! conv_rhs_for_unchecked_shift {
229+
($SelfT:ty, $x:expr) => {{
230+
#[inline]
231+
fn conv(x: u32) -> $SelfT {
232+
// FIXME(const-hack) replace with `.try_into().ok().unwrap_unchecked()`.
233+
// SAFETY: Any legal shift amount must be losslessly representable in the self type.
234+
unsafe { x.try_into().ok().unwrap_unchecked() }
235+
}
236+
#[inline]
237+
const fn const_conv(x: u32) -> $SelfT {
238+
x as _
239+
}
240+
241+
intrinsics::const_eval_select(($x,), const_conv, conv)
242+
}};
243+
}
244+
227245
impl i8 {
228246
int_impl! {
229247
Self = i8,

‎library/core/src/num/uint_macros.rs

+2-4
Original file line numberDiff line numberDiff line change
@@ -939,8 +939,7 @@ macro_rules! uint_impl {
939939
// SAFETY: the caller must uphold the safety contract for
940940
// `unchecked_shl`.
941941
// Any legal shift amount is losslessly representable in the self type.
942-
// FIXME(const-hack) replace with `.try_into().ok().unwrap_unchecked()`.
943-
unsafe { intrinsics::unchecked_shl(self, rhs as _) }
942+
unsafe { intrinsics::unchecked_shl(self, conv_rhs_for_unchecked_shift!($SelfT, rhs)) }
944943
}
945944

946945
/// Checked shift right. Computes `self >> rhs`, returning `None`
@@ -988,8 +987,7 @@ macro_rules! uint_impl {
988987
// SAFETY: the caller must uphold the safety contract for
989988
// `unchecked_shr`.
990989
// Any legal shift amount is losslessly representable in the self type.
991-
// FIXME(const-hack) replace with `.try_into().ok().unwrap_unchecked()`.
992-
unsafe { intrinsics::unchecked_shr(self, rhs as _) }
990+
unsafe { intrinsics::unchecked_shr(self, conv_rhs_for_unchecked_shift!($SelfT, rhs)) }
993991
}
994992

995993
/// Checked exponentiation. Computes `self.pow(exp)`, returning `None` if

‎tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.Inline.diff

+17-7
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,8 @@
1010
+ scope 1 (inlined core::num::<impl u16>::unchecked_shl) { // at $DIR/unchecked_shifts.rs:11:7: 11:23
1111
+ debug self => _3; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
1212
+ debug rhs => _4; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
13-
+ let mut _5: u16; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
13+
+ let mut _5: u16; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
14+
+ let mut _6: (u32,); // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
1415
+ scope 2 {
1516
+ }
1617
+ }
@@ -21,18 +22,27 @@
2122
StorageLive(_4); // scope 0 at $DIR/unchecked_shifts.rs:+1:21: +1:22
2223
_4 = _2; // scope 0 at $DIR/unchecked_shifts.rs:+1:21: +1:22
2324
- _0 = core::num::<impl u16>::unchecked_shl(move _3, move _4) -> bb1; // scope 0 at $DIR/unchecked_shifts.rs:+1:5: +1:23
24-
+ StorageLive(_5); // scope 0 at $DIR/unchecked_shifts.rs:+1:7: +1:23
25-
+ _5 = _4 as u16 (IntToInt); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
26-
+ _0 = unchecked_shl::<u16>(_3, _5) -> [return: bb1, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
25+
+ StorageLive(_5); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
26+
+ StorageLive(_6); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
27+
+ _6 = (_4,); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
28+
+ _5 = core::num::<impl u16>::unchecked_shl::conv(move (_6.0: u32)) -> bb1; // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
2729
// mir::Constant
2830
- // + span: $DIR/unchecked_shifts.rs:11:7: 11:20
2931
- // + literal: Const { ty: unsafe fn(u16, u32) -> u16 {core::num::<impl u16>::unchecked_shl}, val: Value(<ZST>) }
30-
+ // + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
31-
+ // + literal: Const { ty: unsafe extern "rust-intrinsic" fn(u16, u16) -> u16 {unchecked_shl::<u16>}, val: Value(<ZST>) }
32+
+ // + span: $SRC_DIR/core/src/num/mod.rs:LL:COL
33+
+ // + literal: Const { ty: fn(u32) -> u16 {core::num::<impl u16>::unchecked_shl::conv}, val: Value(<ZST>) }
3234
}
3335

3436
bb1: {
35-
+ StorageDead(_5); // scope 0 at $DIR/unchecked_shifts.rs:+1:7: +1:23
37+
+ StorageDead(_6); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
38+
+ _0 = unchecked_shl::<u16>(_3, move _5) -> [return: bb2, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
39+
+ // mir::Constant
40+
+ // + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
41+
+ // + literal: Const { ty: unsafe extern "rust-intrinsic" fn(u16, u16) -> u16 {unchecked_shl::<u16>}, val: Value(<ZST>) }
42+
+ }
43+
+
44+
+ bb2: {
45+
+ StorageDead(_5); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
3646
StorageDead(_4); // scope 0 at $DIR/unchecked_shifts.rs:+1:22: +1:23
3747
StorageDead(_3); // scope 0 at $DIR/unchecked_shifts.rs:+1:22: +1:23
3848
return; // scope 0 at $DIR/unchecked_shifts.rs:+2:2: +2:2

‎tests/mir-opt/inline/unchecked_shifts.unchecked_shl_unsigned_smaller.PreCodegen.after.mir

+16-6
Original file line numberDiff line numberDiff line change
@@ -7,22 +7,32 @@ fn unchecked_shl_unsigned_smaller(_1: u16, _2: u32) -> u16 {
77
scope 1 (inlined core::num::<impl u16>::unchecked_shl) { // at $DIR/unchecked_shifts.rs:11:7: 11:23
88
debug self => _1; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
99
debug rhs => _2; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
10-
let mut _3: u16; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
10+
let mut _3: u16; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
11+
let mut _4: (u32,); // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
1112
scope 2 {
1213
}
1314
}
1415

1516
bb0: {
16-
StorageLive(_3); // scope 0 at $DIR/unchecked_shifts.rs:+1:7: +1:23
17-
_3 = _2 as u16 (IntToInt); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
18-
_0 = unchecked_shl::<u16>(_1, _3) -> [return: bb1, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
17+
StorageLive(_3); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
18+
StorageLive(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
19+
_4 = (_2,); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
20+
_3 = core::num::<impl u16>::unchecked_shl::conv(move (_4.0: u32)) -> bb1; // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
21+
// mir::Constant
22+
// + span: $SRC_DIR/core/src/num/mod.rs:LL:COL
23+
// + literal: Const { ty: fn(u32) -> u16 {core::num::<impl u16>::unchecked_shl::conv}, val: Value(<ZST>) }
24+
}
25+
26+
bb1: {
27+
StorageDead(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
28+
_0 = unchecked_shl::<u16>(_1, move _3) -> [return: bb2, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
1929
// mir::Constant
2030
// + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
2131
// + literal: Const { ty: unsafe extern "rust-intrinsic" fn(u16, u16) -> u16 {unchecked_shl::<u16>}, val: Value(<ZST>) }
2232
}
2333

24-
bb1: {
25-
StorageDead(_3); // scope 0 at $DIR/unchecked_shifts.rs:+1:7: +1:23
34+
bb2: {
35+
StorageDead(_3); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
2636
return; // scope 0 at $DIR/unchecked_shifts.rs:+2:2: +2:2
2737
}
2838
}

‎tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.Inline.diff

+17-7
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,8 @@
1010
+ scope 1 (inlined core::num::<impl i16>::unchecked_shr) { // at $DIR/unchecked_shifts.rs:17:7: 17:23
1111
+ debug self => _3; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
1212
+ debug rhs => _4; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
13-
+ let mut _5: i16; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
13+
+ let mut _5: i16; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
14+
+ let mut _6: (u32,); // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
1415
+ scope 2 {
1516
+ }
1617
+ }
@@ -21,18 +22,27 @@
2122
StorageLive(_4); // scope 0 at $DIR/unchecked_shifts.rs:+1:21: +1:22
2223
_4 = _2; // scope 0 at $DIR/unchecked_shifts.rs:+1:21: +1:22
2324
- _0 = core::num::<impl i16>::unchecked_shr(move _3, move _4) -> bb1; // scope 0 at $DIR/unchecked_shifts.rs:+1:5: +1:23
24-
+ StorageLive(_5); // scope 0 at $DIR/unchecked_shifts.rs:+1:7: +1:23
25-
+ _5 = _4 as i16 (IntToInt); // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
26-
+ _0 = unchecked_shr::<i16>(_3, _5) -> [return: bb1, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
25+
+ StorageLive(_5); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
26+
+ StorageLive(_6); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
27+
+ _6 = (_4,); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
28+
+ _5 = core::num::<impl i16>::unchecked_shr::conv(move (_6.0: u32)) -> bb1; // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
2729
// mir::Constant
2830
- // + span: $DIR/unchecked_shifts.rs:17:7: 17:20
2931
- // + literal: Const { ty: unsafe fn(i16, u32) -> i16 {core::num::<impl i16>::unchecked_shr}, val: Value(<ZST>) }
30-
+ // + span: $SRC_DIR/core/src/num/int_macros.rs:LL:COL
31-
+ // + literal: Const { ty: unsafe extern "rust-intrinsic" fn(i16, i16) -> i16 {unchecked_shr::<i16>}, val: Value(<ZST>) }
32+
+ // + span: $SRC_DIR/core/src/num/mod.rs:LL:COL
33+
+ // + literal: Const { ty: fn(u32) -> i16 {core::num::<impl i16>::unchecked_shr::conv}, val: Value(<ZST>) }
3234
}
3335

3436
bb1: {
35-
+ StorageDead(_5); // scope 0 at $DIR/unchecked_shifts.rs:+1:7: +1:23
37+
+ StorageDead(_6); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
38+
+ _0 = unchecked_shr::<i16>(_3, move _5) -> [return: bb2, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
39+
+ // mir::Constant
40+
+ // + span: $SRC_DIR/core/src/num/int_macros.rs:LL:COL
41+
+ // + literal: Const { ty: unsafe extern "rust-intrinsic" fn(i16, i16) -> i16 {unchecked_shr::<i16>}, val: Value(<ZST>) }
42+
+ }
43+
+
44+
+ bb2: {
45+
+ StorageDead(_5); // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
3646
StorageDead(_4); // scope 0 at $DIR/unchecked_shifts.rs:+1:22: +1:23
3747
StorageDead(_3); // scope 0 at $DIR/unchecked_shifts.rs:+1:22: +1:23
3848
return; // scope 0 at $DIR/unchecked_shifts.rs:+2:2: +2:2

‎tests/mir-opt/inline/unchecked_shifts.unchecked_shr_signed_smaller.PreCodegen.after.mir

+16-6
Original file line numberDiff line numberDiff line change
@@ -7,22 +7,32 @@ fn unchecked_shr_signed_smaller(_1: i16, _2: u32) -> i16 {
77
scope 1 (inlined core::num::<impl i16>::unchecked_shr) { // at $DIR/unchecked_shifts.rs:17:7: 17:23
88
debug self => _1; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
99
debug rhs => _2; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
10-
let mut _3: i16; // in scope 1 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
10+
let mut _3: i16; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
11+
let mut _4: (u32,); // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
1112
scope 2 {
1213
}
1314
}
1415

1516
bb0: {
16-
StorageLive(_3); // scope 0 at $DIR/unchecked_shifts.rs:+1:7: +1:23
17-
_3 = _2 as i16 (IntToInt); // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
18-
_0 = unchecked_shr::<i16>(_1, _3) -> [return: bb1, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
17+
StorageLive(_3); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
18+
StorageLive(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
19+
_4 = (_2,); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
20+
_3 = core::num::<impl i16>::unchecked_shr::conv(move (_4.0: u32)) -> bb1; // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
21+
// mir::Constant
22+
// + span: $SRC_DIR/core/src/num/mod.rs:LL:COL
23+
// + literal: Const { ty: fn(u32) -> i16 {core::num::<impl i16>::unchecked_shr::conv}, val: Value(<ZST>) }
24+
}
25+
26+
bb1: {
27+
StorageDead(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
28+
_0 = unchecked_shr::<i16>(_1, move _3) -> [return: bb2, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
1929
// mir::Constant
2030
// + span: $SRC_DIR/core/src/num/int_macros.rs:LL:COL
2131
// + literal: Const { ty: unsafe extern "rust-intrinsic" fn(i16, i16) -> i16 {unchecked_shr::<i16>}, val: Value(<ZST>) }
2232
}
2333

24-
bb1: {
25-
StorageDead(_3); // scope 0 at $DIR/unchecked_shifts.rs:+1:7: +1:23
34+
bb2: {
35+
StorageDead(_3); // scope 2 at $SRC_DIR/core/src/num/int_macros.rs:LL:COL
2636
return; // scope 0 at $DIR/unchecked_shifts.rs:+2:2: +2:2
2737
}
2838
}

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