Skip to content

Commit 76155af

Browse files
authored
Merge pull request #753 from rust-embedded/refac
small refactoring and release 0.30.2
2 parents 52a9b48 + 5e9a29c commit 76155af

File tree

7 files changed

+42
-67
lines changed

7 files changed

+42
-67
lines changed

CHANGELOG.md

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
77

88
## [Unreleased]
99

10+
## [v0.30.2] - 2023-10-22
11+
12+
- Fix documentation warnings
1013
- Use `ArrayProxy` for memory disjoined register arrays
1114
- Use `const fn` where allowed
1215

@@ -813,7 +816,8 @@ peripheral.register.write(|w| w.field().set());
813816

814817
- Initial version of the `svd2rust` tool
815818

816-
[Unreleased]: https://github.com/rust-embedded/svd2rust/compare/v0.30.1...HEAD
819+
[Unreleased]: https://github.com/rust-embedded/svd2rust/compare/v0.30.2...HEAD
820+
[v0.30.2]: https://github.com/rust-embedded/svd2rust/compare/v0.30.1...v0.30.2
817821
[v0.30.1]: https://github.com/rust-embedded/svd2rust/compare/v0.30.0...v0.30.1
818822
[v0.30.0]: https://github.com/rust-embedded/svd2rust/compare/v0.29.0...v0.30.0
819823
[v0.29.0]: https://github.com/rust-embedded/svd2rust/compare/v0.28.0...v0.29.0

Cargo.lock

Lines changed: 1 addition & 1 deletion
Some generated files are not rendered by default. Learn more about customizing how changed files appear on GitHub.

Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ keywords = [
2323
license = "MIT OR Apache-2.0"
2424
name = "svd2rust"
2525
repository = "https://github.com/rust-embedded/svd2rust/"
26-
version = "0.30.1"
26+
version = "0.30.2"
2727
readme = "README.md"
2828
rust-version = "1.70"
2929

src/generate/generic.rs

Lines changed: 32 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -457,18 +457,50 @@ impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI>
457457
where
458458
REG: Writable + RegisterSpec,
459459
FI: FieldSpec,
460+
REG::Ux: From<FI::Ux>,
460461
{
461462
/// Field width
462463
pub const WIDTH: u8 = WI;
464+
465+
/// Writes raw bits to the field
466+
///
467+
/// # Safety
468+
///
469+
/// Passing incorrect value can cause undefined behaviour. See reference manual
470+
#[inline(always)]
471+
pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
472+
self.w.bits &= !(REG::Ux::mask::<WI>() << OF);
473+
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << OF;
474+
self.w
475+
}
476+
/// Writes `variant` to the field
477+
#[inline(always)]
478+
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
479+
unsafe { self.bits(FI::Ux::from(variant)) }
480+
}
463481
}
464482

465483
impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI>
466484
where
467485
REG: Writable + RegisterSpec,
468486
FI: FieldSpec,
487+
REG::Ux: From<FI::Ux>,
469488
{
470489
/// Field width
471490
pub const WIDTH: u8 = WI;
491+
492+
/// Writes raw bits to the field
493+
#[inline(always)]
494+
pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
495+
self.w.bits &= !(REG::Ux::mask::<WI>() << OF);
496+
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << OF;
497+
self.w
498+
}
499+
/// Writes `variant` to the field
500+
#[inline(always)]
501+
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
502+
self.bits(FI::Ux::from(variant))
503+
}
472504
}
473505

474506
macro_rules! bit_proxy {
@@ -486,17 +518,7 @@ macro_rules! bit_proxy {
486518
{
487519
/// Field width
488520
pub const WIDTH: u8 = 1;
489-
}
490-
};
491-
}
492521

493-
macro_rules! impl_bit_proxy {
494-
($writer:ident) => {
495-
impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI>
496-
where
497-
REG: Writable + RegisterSpec,
498-
bool: From<FI>,
499-
{
500522
/// Writes bit to the field
501523
#[inline(always)]
502524
pub fn bit(self, value: bool) -> &'a mut W<REG> {
@@ -521,57 +543,6 @@ bit_proxy!(BitWriter0S, Bit0S);
521543
bit_proxy!(BitWriter1T, Bit1T);
522544
bit_proxy!(BitWriter0T, Bit0T);
523545

524-
impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI>
525-
where
526-
REG: Writable + RegisterSpec,
527-
FI: FieldSpec,
528-
REG::Ux: From<FI::Ux>,
529-
{
530-
/// Writes raw bits to the field
531-
///
532-
/// # Safety
533-
///
534-
/// Passing incorrect value can cause undefined behaviour. See reference manual
535-
#[inline(always)]
536-
pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
537-
self.w.bits &= !(REG::Ux::mask::<WI>() << OF);
538-
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << OF;
539-
self.w
540-
}
541-
/// Writes `variant` to the field
542-
#[inline(always)]
543-
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
544-
unsafe { self.bits(FI::Ux::from(variant)) }
545-
}
546-
}
547-
impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriterSafe<'a, REG, WI, OF, FI>
548-
where
549-
REG: Writable + RegisterSpec,
550-
FI: FieldSpec,
551-
REG::Ux: From<FI::Ux>,
552-
{
553-
/// Writes raw bits to the field
554-
#[inline(always)]
555-
pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
556-
self.w.bits &= !(REG::Ux::mask::<WI>() << OF);
557-
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << OF;
558-
self.w
559-
}
560-
/// Writes `variant` to the field
561-
#[inline(always)]
562-
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
563-
self.bits(FI::Ux::from(variant))
564-
}
565-
}
566-
567-
impl_bit_proxy!(BitWriter);
568-
impl_bit_proxy!(BitWriter1S);
569-
impl_bit_proxy!(BitWriter0C);
570-
impl_bit_proxy!(BitWriter1C);
571-
impl_bit_proxy!(BitWriter0S);
572-
impl_bit_proxy!(BitWriter1T);
573-
impl_bit_proxy!(BitWriter0T);
574-
575546
impl<'a, REG, const OF: u8, FI> BitWriter<'a, REG, OF, FI>
576547
where
577548
REG: Writable + RegisterSpec,

src/generate/register.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ pub fn render(
9595
);
9696
if name_snake_case != "cfg" {
9797
alias_doc += format!(
98-
"\n\nFor information about available fields see [`{name_snake_case}`] module"
98+
"\n\nFor information about available fields see [`mod@{name_snake_case}`] module"
9999
)
100100
.as_str();
101101
}

src/lib.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -588,7 +588,7 @@ pub fn generate(input: &str, config: &Config) -> Result<Generation> {
588588
})
589589
}
590590

591-
/// Load a [Device] from a string slice with given [config](crate::util::Config).
591+
/// Load a [Device](svd::Device) from a string slice with given [config](crate::util::Config).
592592
pub fn load_from(input: &str, config: &crate::util::Config) -> Result<svd::Device> {
593593
use self::util::SourceType;
594594
use svd_parser::ValidateLevel;

src/util.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -183,7 +183,7 @@ pub enum SourceType {
183183
}
184184

185185
impl SourceType {
186-
/// Make a new [`Source`] from a given extension.
186+
/// Make a new [`SourceType`] from a given extension.
187187
pub fn from_extension(s: &str) -> Option<Self> {
188188
match s {
189189
"svd" | "xml" => Some(Self::Xml),

0 commit comments

Comments
 (0)