Skip to content

Commit 909a68b

Browse files
authored
Merge pull request #276 from romancardenas/master
Revert riscv elements and unstable-riscv feature
2 parents b6c183e + f7f47bf commit 909a68b

21 files changed

+8
-1060
lines changed

svd-encoder/CHANGELOG.md

+2
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
77

88
## Unreleased
99

10+
- Revert the `riscv` element, as well as the `unstable-riscv` feature.
11+
1012
## [v0.14.5] - 2023-08-20
1113

1214
- Adapt the `riscv` element to handle `riscv::Exception`.

svd-encoder/Cargo.toml

-3
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,6 @@ rust-version = "1.65.0"
1111
version = "0.14.5"
1212
readme = "README.md"
1313

14-
[features]
15-
unstable-riscv = ["svd-rs/unstable-riscv"]
16-
1714
[dependencies]
1815
convert_case = "0.6.0"
1916
svd-rs = { version = "0.14.9", path = "../svd-rs" }

svd-encoder/src/device.rs

-6
Original file line numberDiff line numberDiff line change
@@ -34,12 +34,6 @@ impl Encode for Device {
3434
elem.children.push(new_node("licenseText", v.clone()));
3535
}
3636

37-
#[cfg(feature = "unstable-riscv")]
38-
if let Some(v) = &self.riscv {
39-
elem.children
40-
.push(XMLNode::Element(v.encode_with_config(config)?));
41-
}
42-
4337
if let Some(v) = &self.cpu {
4438
elem.children
4539
.push(XMLNode::Element(v.encode_with_config(config)?));

svd-encoder/src/lib.rs

-2
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,5 @@ mod readaction;
103103
mod register;
104104
mod registercluster;
105105
mod registerproperties;
106-
#[cfg(feature = "unstable-riscv")]
107-
mod riscv;
108106
mod usage;
109107
mod writeconstraint;

svd-encoder/src/riscv.rs

-95
This file was deleted.

svd-parser/CHANGELOG.md

+4
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,10 @@ All notable changes to this project will be documented in this file.
55
The format is based on [Keep a Changelog](http://keepachangelog.com/)
66
and this project adheres to [Semantic Versioning](http://semver.org/).
77

8+
## Unreleased
9+
10+
- Revert the `riscv` element, as well as the `unstable-riscv` feature.
11+
812
## [v0.14.7] - 2024-10-03
913

1014
- Bump svd-rs to 0.14.9

svd-parser/Cargo.toml

-1
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@ readme = "README.md"
1717
[features]
1818
derive-from = ["svd-rs/derive-from"]
1919
expand = ["derive-from"]
20-
unstable-riscv = ["svd-rs/unstable-riscv"]
2120

2221
[dependencies]
2322
svd-rs = { version = "0.14.9", path = "../svd-rs" }

svd-parser/src/device.rs

-6
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,4 @@
11
use super::*;
2-
#[cfg(feature = "unstable-riscv")]
3-
use crate::svd::riscv::Riscv;
42
use crate::svd::{cpu::Cpu, peripheral::Peripheral, registerproperties::RegisterProperties};
53

64
/// Parses a SVD file
@@ -33,10 +31,6 @@ impl Parse for Device {
3331
.collect();
3432
ps?
3533
});
36-
#[cfg(feature = "unstable-riscv")]
37-
if let Some(riscv) = optional::<Riscv>("riscv", tree, config)? {
38-
device = device.riscv(riscv);
39-
}
4034
if let Some(version) = tree.get_child_text_opt("version")? {
4135
device = device.version(version)
4236
}

svd-parser/src/lib.rs

-2
Original file line numberDiff line numberDiff line change
@@ -211,8 +211,6 @@ mod readaction;
211211
mod register;
212212
mod registercluster;
213213
mod registerproperties;
214-
#[cfg(feature = "unstable-riscv")]
215-
mod riscv;
216214
mod usage;
217215
mod writeconstraint;
218216

svd-parser/src/riscv.rs

-113
This file was deleted.

svd-rs/CHANGELOG.md

+2
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
77

88
## Unreleased
99

10+
- Revert the `riscv` elements, as well as the `unstable-riscv` feature.
11+
1012
## [v0.14.9] - 2024-08-20
1113

1214
- Add `riscv::Exception` for custom exception source enumerations.

svd-rs/Cargo.toml

-1
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@ readme = "README.md"
1515

1616
[features]
1717
derive-from = []
18-
unstable-riscv = []
1918

2019
[dependencies]
2120
thiserror = "1.0.31"

svd-rs/src/device.rs

-26
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
#[cfg(feature = "unstable-riscv")]
2-
use super::Riscv;
31
use super::{
42
BuildError, Cpu, Description, EmptyToNone, Name, Peripheral, RegisterProperties, SvdError,
53
ValidateLevel,
@@ -107,14 +105,6 @@ pub struct Device {
107105
/// Specify the compliant CMSIS-SVD schema version
108106
#[cfg_attr(feature = "serde", serde(skip, default = "default_schema_version"))]
109107
pub schema_version: String,
110-
111-
/// Describe the processor included in the device
112-
#[cfg_attr(
113-
feature = "serde",
114-
serde(default, skip_serializing_if = "Option::is_none")
115-
)]
116-
#[cfg(feature = "unstable-riscv")]
117-
pub riscv: Option<Riscv>,
118108
}
119109

120110
fn default_xmlns_xs() -> String {
@@ -140,8 +130,6 @@ pub struct DeviceBuilder {
140130
version: Option<String>,
141131
description: Option<String>,
142132
license_text: Option<String>,
143-
#[cfg(feature = "unstable-riscv")]
144-
riscv: Option<Riscv>,
145133
cpu: Option<Cpu>,
146134
header_system_filename: Option<String>,
147135
header_definitions_prefix: Option<String>,
@@ -164,8 +152,6 @@ impl From<Device> for DeviceBuilder {
164152
version: Some(d.version),
165153
description: Some(d.description),
166154
license_text: d.license_text,
167-
#[cfg(feature = "unstable-riscv")]
168-
riscv: d.riscv,
169155
cpu: d.cpu,
170156
header_system_filename: d.header_system_filename,
171157
header_definitions_prefix: d.header_definitions_prefix,
@@ -216,12 +202,6 @@ impl DeviceBuilder {
216202
self.license_text = value;
217203
self
218204
}
219-
/// Set the riscv of the device.
220-
#[cfg(feature = "unstable-riscv")]
221-
pub fn riscv(mut self, value: Riscv) -> Self {
222-
self.riscv = Some(value);
223-
self
224-
}
225205
/// Set the cpu of the device.
226206
pub fn cpu(mut self, value: Option<Cpu>) -> Self {
227207
self.cpu = value;
@@ -303,8 +283,6 @@ impl DeviceBuilder {
303283
})
304284
.ok_or_else(|| BuildError::Uninitialized("description".to_string()))?,
305285
license_text: self.license_text,
306-
#[cfg(feature = "unstable-riscv")]
307-
riscv: self.riscv,
308286
cpu: self.cpu,
309287
header_system_filename: self.header_system_filename,
310288
header_definitions_prefix: self.header_definitions_prefix,
@@ -363,10 +341,6 @@ impl Device {
363341
if builder.license_text.is_some() {
364342
self.license_text = builder.license_text.empty_to_none();
365343
}
366-
#[cfg(feature = "unstable-riscv")]
367-
if builder.riscv.is_some() {
368-
self.riscv = builder.riscv;
369-
}
370344
if builder.cpu.is_some() {
371345
self.cpu = builder.cpu;
372346
}

svd-rs/src/lib.rs

-6
Original file line numberDiff line numberDiff line change
@@ -94,12 +94,6 @@ pub use self::protection::Protection;
9494
pub mod datatype;
9595
pub use self::datatype::DataType;
9696

97-
/// Custom objects for the RISC-V ecosystem
98-
#[cfg(feature = "unstable-riscv")]
99-
pub mod riscv;
100-
#[cfg(feature = "unstable-riscv")]
101-
pub use self::riscv::Riscv;
102-
10397
/// Level of validation
10498
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10599
pub enum ValidateLevel {

0 commit comments

Comments
 (0)