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2 parents b23a94f + 858f2db commit f7afa99Copy full SHA for f7afa99
riscv-rt/macros/src/lib.rs
@@ -483,12 +483,14 @@ fn vectored_interrupt_trap(arch: RiscvArch) -> TokenStream {
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core::arch::global_asm!(
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".section .trap, \"ax\"
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+.align 4
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.global _start_DefaultHandler_trap
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_start_DefaultHandler_trap:
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addi sp, sp, -{TRAP_SIZE} * {width} // allocate space for trap frame
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{store_start} // store trap partially (only register a0)
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la a0, DefaultHandler // load interrupt handler address into a0
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.global _continue_interrupt_trap
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_continue_interrupt_trap:
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{store_continue} // store trap partially (all registers except a0)
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