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Merge pull request #207 from jsgf/mstatus-field-set
Add Mstatus helpers to allow setting fields in Mstatus
2 parents b77662f + a2a9888 commit e9f43ae

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6 files changed

+301
-27
lines changed

6 files changed

+301
-27
lines changed

riscv/CHANGELOG.md

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@@ -13,6 +13,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Add `Mstatus::from(usize)` for use in unit tests
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- Add `Mstatus.bits()`
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- Add `Eq` and `PartialEq` for `pmpcfgx::{Range, Permission}`
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- Add `Mstatus::update_*` helpers to manipulate Mstatus values without touching
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the CSR
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- Export `riscv::register::macros` module macros for external use
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### Fixed

riscv/src/bits.rs

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@@ -0,0 +1,17 @@
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/// Insert a new value into a bitfield
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///
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/// `value` is masked to `width` bits and inserted into `orig`.`
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#[inline]
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pub fn bf_insert(orig: usize, bit: usize, width: usize, value: usize) -> usize {
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let mask = (1 << width) - 1;
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orig & !(mask << bit) | ((value & mask) << bit)
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}
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/// Extract a value from a bitfield
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///
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/// Extracts `width` bits from bit offset `bit` and returns it shifted to bit 0.s
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#[inline]
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pub fn bf_extract(orig: usize, bit: usize, width: usize) -> usize {
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let mask = (1 << width) - 1;
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(orig >> bit) & mask
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}

riscv/src/lib.rs

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@@ -36,6 +36,7 @@
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#![allow(clippy::missing_safety_doc)]
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pub mod asm;
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pub(crate) mod bits;
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pub mod delay;
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pub mod interrupt;
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pub mod register;

riscv/src/register/macros.rs

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@@ -160,6 +160,34 @@ macro_rules! write_csr_rv32 {
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};
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}
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/// Convenience macro to write a value with `bits` to a CSR
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#[macro_export]
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macro_rules! write_csr_as {
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($csr_type:ty, $csr_number:literal) => {
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$crate::write_csr!($csr_number);
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/// Writes the CSR
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#[inline]
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pub fn write(value: $csr_type) {
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unsafe { _write(value.bits) }
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}
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};
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}
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/// Convenience macro to write a value to a CSR register.
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#[macro_export]
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macro_rules! write_csr_as_rv32 {
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($csr_type:ty, $csr_number:literal) => {
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$crate::write_csr_rv32!($csr_number);
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/// Writes the CSR
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#[inline]
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pub fn write(value: $csr_type) {
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unsafe { _write(value.bits) }
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}
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};
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}
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/// Convenience macro to write a [`usize`] value to a CSR register.
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#[macro_export]
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macro_rules! write_csr_as_usize {

riscv/src/register/misa.rs

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@@ -11,9 +11,9 @@ pub struct Misa {
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/// Base integer ISA width
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum XLEN {
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XLEN32,
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XLEN64,
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XLEN128,
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XLEN32 = 1,
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XLEN64 = 2,
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XLEN128 = 3,
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}
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impl XLEN {

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