riscv: use CSR macros for mcounteren

Uses CSR helper macros to define the `mcounteren` register.

Author: rmsyn

riscv/CHANGELOG.md

@@ -15,6 +15,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Use CSR helper macros to define `marchid` register
 - Re-use `try_*` functions in `mcountinhibit`
+- Use CSR helper macros to define `mcounteren` register
 
 ## [v0.12.1] - 2024-10-20
 

riscv/src/register/mcounteren.rs

@@ -1,113 +1,37 @@
 //! mcounteren register
 
-use crate::bits::{bf_extract, bf_insert};
 use crate::result::{Error, Result};
 
-/// mcounteren register
-#[derive(Clone, Copy, Debug)]
-pub struct Mcounteren {
-    bits: usize,
+read_write_csr! {
+    /// `mcounteren` register
+    Mcounteren: 0x306,
+    mask: 0xffff_ffff,
 }
 
-impl Mcounteren {
+read_write_csr_field! {
+    Mcounteren,
     /// Supervisor "cycle\[h\]" Enable
-    #[inline]
-    pub fn cy(&self) -> bool {
-        bf_extract(self.bits, 0, 1) != 0
-    }
-
-    /// Sets whether to enable the "cycle\[h\]" counter.
-    ///
-    /// Only updates the in-memory value, does not modify the `mcounteren` register.
-    #[inline]
-    pub fn set_cy(&mut self, cy: bool) {
-        self.bits = bf_insert(self.bits, 0, 1, cy as usize);
-    }
+    cy: 0,
+}
 
+read_write_csr_field! {
+    Mcounteren,
     /// Supervisor "time\[h\]" Enable
-    #[inline]
-    pub fn tm(&self) -> bool {
-        bf_extract(self.bits, 1, 1) != 0
-    }
-
-    /// Sets whether to enable "time\[h\]".
-    ///
-    /// Only updates the in-memory value, does not modify the `mcounteren` register.
-    #[inline]
-    pub fn set_tm(&mut self, tm: bool) {
-        self.bits = bf_insert(self.bits, 1, 1, tm as usize);
-    }
+    tm: 1,
+}
 
+read_write_csr_field! {
+    Mcounteren,
     /// Supervisor "instret\[h\]" Enable
-    #[inline]
-    pub fn ir(&self) -> bool {
-        bf_extract(self.bits, 2, 1) != 0
-    }
-
-    /// Sets whether to enable the "instret\[h\]" counter.
-    ///
-    /// Only updates the in-memory value, does not modify the `mcounteren` register.
-    #[inline]
-    pub fn set_ir(&mut self, ir: bool) {
-        self.bits = bf_insert(self.bits, 2, 1, ir as usize);
-    }
+    ir: 2,
+}
 
+read_write_csr_field! {
+    Mcounteren,
     /// Supervisor "hpm\[x\]" Enable (bits 3-31)
-    ///
-    /// **WARNING**: panics on `index` out-of-bounds
-    #[inline]
-    pub fn hpm(&self, index: usize) -> bool {
-        self.try_hpm(index).unwrap()
-    }
-
-    /// Fallible Supervisor "hpm\[x\]" Enable (bits 3-31).
-    ///
-    /// Attempts to read the "hpm\[x\]" value, and returns an error if the `index` is invalid.
-    #[inline]
-    pub fn try_hpm(&self, index: usize) -> Result<bool> {
-        if (3..32).contains(&index) {
-            Ok(bf_extract(self.bits, index, 1) != 0)
-        } else {
-            Err(Error::IndexOutOfBounds {
-                index,
-                min: 3,
-                max: 31,
-            })
-        }
-    }
-
-    /// Sets whether to enable the "hpm\[X\]" counter.
-    ///
-    /// Only updates the in-memory value, does not modify the `mcounteren` register.
-    ///
-    /// **WARNING**: panics on `index` out-of-bounds
-    #[inline]
-    pub fn set_hpm(&mut self, index: usize, hpm: bool) {
-        self.try_set_hpm(index, hpm).unwrap()
-    }
-
-    /// Sets whether to enable the "hpm\[X\]" counter.
-    ///
-    /// Only updates the in-memory value, does not modify the `mcounteren` register.
-    ///
-    /// Attempts to update the "hpm\[x\]" value, and returns an error if the `index` is invalid.
-    #[inline]
-    pub fn try_set_hpm(&mut self, index: usize, hpm: bool) -> Result<()> {
-        if (3..32).contains(&index) {
-            self.bits = bf_insert(self.bits, index, 1, hpm as usize);
-            Ok(())
-        } else {
-            Err(Error::IndexOutOfBounds {
-                index,
-                min: 3,
-                max: 31,
-            })
-        }
-    }
+    hpm: 3..=31,
 }
 
-read_csr_as!(Mcounteren, 0x306);
-write_csr_as!(Mcounteren, 0x306);
 set!(0x306);
 clear!(0x306);