@@ -17,33 +17,85 @@ use super::SCB;
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pub struct RegisterBlock {
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/// Interrupt Control and State
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pub icsr : RW < u32 > ,
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- /// Vector Table Offset
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+
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+ /// Vector Table Offset (not present on Cortex-M0 variants)
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+ #[ cfg( not( armv6m) ) ]
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pub vtor : RW < u32 > ,
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+ #[ cfg( armv6m) ]
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+ _reserved0 : u32 ,
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+
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/// Application Interrupt and Reset Control
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pub aircr : RW < u32 > ,
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+
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/// System Control
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pub scr : RW < u32 > ,
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+
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/// Configuration and Control
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pub ccr : RW < u32 > ,
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- /// System Handler Priority
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+
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+ /// System Handler Priority (word accessible only on Cortex-M0 variants)
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+ ///
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+ /// On ARMv7-M, `shpr[0]` points to SHPR1
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+ ///
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+ /// On ARMv6-M, `shpr[0]` points to SHPR2
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+ #[ cfg( not( armv6m) ) ]
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pub shpr : [ RW < u8 > ; 12 ] ,
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+ #[ cfg( armv6m) ]
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+ _reserved1 : u32 ,
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+ /// System Handler Priority (word accessible only on Cortex-M0 variants)
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+ ///
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+ /// On ARMv7-M, `shpr[0]` points to SHPR1
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+ ///
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+ /// On ARMv6-M, `shpr[0]` points to SHPR2
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+ #[ cfg( armv6m) ]
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+ pub shpr : [ RW < u32 > ; 2 ] ,
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+
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/// System Handler Control and State
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- pub shpcrs : RW < u32 > ,
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- /// Configurable Fault Status
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+ pub shcrs : RW < u32 > ,
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+
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+ /// Configurable Fault Status (not present on Cortex-M0 variants)
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+ #[ cfg( not( armv6m) ) ]
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pub cfsr : RW < u32 > ,
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- /// HardFault Status
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+ #[ cfg( armv6m) ]
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+ _reserved2 : u32 ,
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+
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+ /// HardFault Status (not present on Cortex-M0 variants)
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+ #[ cfg( not( armv6m) ) ]
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pub hfsr : RW < u32 > ,
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- /// Debug Fault Status
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+ #[ cfg( armv6m) ]
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+ _reserved3 : u32 ,
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+
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+ /// Debug Fault Status (not present on Cortex-M0 variants)
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+ #[ cfg( not( armv6m) ) ]
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pub dfsr : RW < u32 > ,
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- /// MemManage Fault Address
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- pub mmar : RW < u32 > ,
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- /// BusFault Address
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+ #[ cfg( armv6m) ]
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+ _reserved4 : u32 ,
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+
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+ /// MemManage Fault Address (not present on Cortex-M0 variants)
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+ #[ cfg( not( armv6m) ) ]
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+ pub mmfar : RW < u32 > ,
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+ #[ cfg( armv6m) ]
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+ _reserved5 : u32 ,
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+
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+ /// BusFault Address (not present on Cortex-M0 variants)
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+ #[ cfg( not( armv6m) ) ]
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pub bfar : RW < u32 > ,
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- /// Auxiliary Fault Status
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+ #[ cfg( armv6m) ]
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+ _reserved6 : u32 ,
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+
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+ /// Auxiliary Fault Status (not present on Cortex-M0 variants)
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+ #[ cfg( not( armv6m) ) ]
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pub afsr : RW < u32 > ,
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- reserved : [ u32 ; 18 ] ,
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- /// Coprocessor Access Control
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+ #[ cfg( armv6m) ]
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+ _reserved7 : u32 ,
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+
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+ _reserved8 : [ u32 ; 18 ] ,
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+
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+ /// Coprocessor Access Control (not present on Cortex-M0 variants)
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+ #[ cfg( not( armv6m) ) ]
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pub cpacr : RW < u32 > ,
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+ #[ cfg( armv6m) ]
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+ _reserved9 : u32 ,
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}
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/// FPU access mode
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