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1 parent 4e9bcf5 commit 42c950dCopy full SHA for 42c950d
src/peripheral/itm.rs
@@ -337,11 +337,14 @@ impl ITM {
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unsafe {
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self.tcr.modify(|mut r| {
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- r.set_itmena(settings.enable);
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r.set_tsena(settings.local_timestamps != LocalTimestampOptions::Disabled);
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r.set_txena(settings.forward_dwt); // forward hardware event packets from the DWT to the ITM
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r.set_tracebusid(settings.bus_id.unwrap_or(0));
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+ // must be modified after TraceBusID, see last section in
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+ // <https://developer.arm.com/documentation/ddi0403/d/Debug-Architecture/ARMv7-M-Debug/The-Instrumentation-Trace-Macrocell/Trace-Control-Register--ITM-TCR?lang=en>
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+ r.set_itmena(settings.enable);
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+
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r
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});
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}
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