Make all available NVIC registers accessible

According to the ARMv7-M Technical Reference Manual[1], there are 124
IPR registers available on ARMv7-M, and 16 of all others. I don't know
where the original numbers came from, since on ARMv6-M, there are only 8
IPR registers available, and 1 of each of the others.[2]

This commit removes some test cases that were checking the address of
the last register. Since the last register has changed, those are no
longer applicable. I decided to remove instead of update them, since
they only really test the length of each register type, which is obvious
enough from the code.

[1]: https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR580-DA-70000-r0p0-05rel0/DDI0403E_B_armv7m_arm.pdf
[2]: https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR585-DA-70000-r0p0-00rel0/DDI0419C_arm_architecture_v6m_reference_manual.pdf

Author: hannobraun

src/peripheral/nvic.rs

@@ -8,22 +8,22 @@ use interrupt::Nr;
 #[repr(C)]
 pub struct RegisterBlock {
     /// Interrupt Set-Enable
-    pub iser: [RW<u32>; 8],
-    reserved0: [u32; 24],
+    pub iser: [RW<u32>; 16],
+    reserved0: [u32; 16],
     /// Interrupt Clear-Enable
-    pub icer: [RW<u32>; 8],
-    reserved1: [u32; 24],
+    pub icer: [RW<u32>; 16],
+    reserved1: [u32; 16],
     /// Interrupt Set-Pending
-    pub ispr: [RW<u32>; 8],
-    reserved2: [u32; 24],
+    pub ispr: [RW<u32>; 16],
+    reserved2: [u32; 16],
     /// Interrupt Clear-Pending
-    pub icpr: [RW<u32>; 8],
-    reserved3: [u32; 24],
+    pub icpr: [RW<u32>; 16],
+    reserved3: [u32; 16],
     /// Interrupt Active Bit
-    pub iabr: [RO<u32>; 8],
-    reserved4: [u32; 56],
+    pub iabr: [RO<u32>; 16],
+    reserved4: [u32; 48],
     /// Interrupt Priority
-    pub ipr: [RW<u8>; 240],
+    pub ipr: [RW<u8>; 496],
 }
 
 impl RegisterBlock {

src/peripheral/test.rs

@@ -104,17 +104,11 @@ fn nvic() {
     let nvic = unsafe { &*::peripheral::NVIC::ptr() };
 
     assert_eq!(address(&nvic.iser), 0xE000E100);
-    assert_eq!(address(&nvic.iser[7]), 0xE000E11C);
     assert_eq!(address(&nvic.icer), 0xE000E180);
-    assert_eq!(address(&nvic.icer[7]), 0xE000E19C);
     assert_eq!(address(&nvic.ispr), 0xE000E200);
-    assert_eq!(address(&nvic.ispr[7]), 0xE000E21C);
     assert_eq!(address(&nvic.icpr), 0xE000E280);
-    assert_eq!(address(&nvic.icpr[7]), 0xE000E29C);
     assert_eq!(address(&nvic.iabr), 0xE000E300);
-    assert_eq!(address(&nvic.iabr[7]), 0xE000E31C);
     assert_eq!(address(&nvic.ipr), 0xE000E400);
-    assert_eq!(address(&nvic.ipr[239]), 0xE000E4eF);
 }
 
 #[test]