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Merge #28
28: bump the cortex-m-rt to v0.4.0 r=japaric a=japaric Co-authored-by: Jorge Aparicio <[email protected]>
2 parents 6f62705 + a18a2fe commit 43acbc4

23 files changed

+281
-164
lines changed

.cargo/config

+16-12
Original file line numberDiff line numberDiff line change
@@ -2,34 +2,38 @@
22
runner = 'arm-none-eabi-gdb'
33
rustflags = [
44
"-C", "link-arg=-Tlink.x",
5-
"-C", "linker=arm-none-eabi-ld",
6-
"-Z", "linker-flavor=ld",
7-
"-Z", "thinlto=no",
5+
"-C", "linker=lld",
6+
"-Z", "linker-flavor=ld.lld",
7+
# "-C", "linker=arm-none-eabi-ld",
8+
# "-Z", "linker-flavor=ld",
89
]
910

1011
[target.thumbv7m-none-eabi]
1112
runner = 'arm-none-eabi-gdb'
1213
rustflags = [
1314
"-C", "link-arg=-Tlink.x",
14-
"-C", "linker=arm-none-eabi-ld",
15-
"-Z", "linker-flavor=ld",
16-
"-Z", "thinlto=no",
15+
"-C", "linker=lld",
16+
"-Z", "linker-flavor=ld.lld",
17+
# "-C", "linker=arm-none-eabi-ld",
18+
# "-Z", "linker-flavor=ld",
1719
]
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1921
[target.thumbv7em-none-eabi]
2022
runner = 'arm-none-eabi-gdb'
2123
rustflags = [
2224
"-C", "link-arg=-Tlink.x",
23-
"-C", "linker=arm-none-eabi-ld",
24-
"-Z", "linker-flavor=ld",
25-
"-Z", "thinlto=no",
25+
"-C", "linker=lld",
26+
"-Z", "linker-flavor=ld.lld",
27+
# "-C", "linker=arm-none-eabi-ld",
28+
# "-Z", "linker-flavor=ld",
2629
]
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2831
[target.thumbv7em-none-eabihf]
2932
runner = 'arm-none-eabi-gdb'
3033
rustflags = [
3134
"-C", "link-arg=-Tlink.x",
32-
"-C", "linker=arm-none-eabi-ld",
33-
"-Z", "linker-flavor=ld",
34-
"-Z", "thinlto=no",
35+
"-C", "linker=lld",
36+
"-Z", "linker-flavor=ld.lld",
37+
# "-C", "linker=arm-none-eabi-ld",
38+
# "-Z", "linker-flavor=ld",
3539
]

.travis.yml

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@@ -0,0 +1,64 @@
1+
language: rust
2+
3+
matrix:
4+
include:
5+
- env: TARGET=thumbv6m-none-eabi
6+
rust: nightly
7+
addons:
8+
apt:
9+
sources:
10+
- debian-sid
11+
packages:
12+
- binutils-arm-none-eabi
13+
14+
- env: TARGET=thumbv7m-none-eabi
15+
rust: nightly
16+
addons:
17+
apt:
18+
sources:
19+
- debian-sid
20+
packages:
21+
- binutils-arm-none-eabi
22+
23+
- env: TARGET=thumbv7em-none-eabi
24+
rust: nightly
25+
addons:
26+
apt:
27+
sources:
28+
- debian-sid
29+
packages:
30+
- binutils-arm-none-eabi
31+
32+
- env: TARGET=thumbv7em-none-eabihf
33+
rust: nightly
34+
addons:
35+
apt:
36+
sources:
37+
- debian-sid
38+
packages:
39+
- binutils-arm-none-eabi
40+
41+
before_install: set -e
42+
43+
install:
44+
- bash ci/install.sh
45+
46+
script:
47+
- bash ci/script.sh
48+
49+
after_script: set +e
50+
51+
cache: cargo
52+
53+
before_cache:
54+
# Travis can't cache files that are not readable by "others"
55+
- chmod -R a+r $HOME/.cargo
56+
57+
branches:
58+
only:
59+
- staging
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- trying
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62+
notifications:
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email:
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on_success: never

CHANGELOG.md

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@@ -5,6 +5,12 @@ This project adheres to [Semantic Versioning](http://semver.org/).
55

66
## [Unreleased]
77

8+
## [v0.2.7] - 2018-04-24
9+
10+
### Changed
11+
12+
- Bumped the dependency of `cortex-m-rt` to v0.4.0.
13+
814
## [v0.2.6] - 2018-04-09
915

1016
### Changed
@@ -143,7 +149,8 @@ This project adheres to [Semantic Versioning](http://semver.org/).
143149

144150
- Initial release
145151

146-
[Unreleased]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.6...HEAD
152+
[Unreleased]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.7...HEAD
153+
[v0.2.7]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.6...v0.2.7
147154
[v0.2.6]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.5...v0.2.6
148155
[v0.2.5]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.4...v0.2.5
149156
[v0.2.4]: https://github.com/japaric/cortex-m-quickstart/compare/v0.2.3...v0.2.4

Cargo.toml

+7-9
Original file line numberDiff line numberDiff line change
@@ -6,25 +6,23 @@ keywords = ["arm", "cortex-m", "template"]
66
license = "MIT OR Apache-2.0"
77
name = "cortex-m-quickstart"
88
repository = "https://github.com/japaric/cortex-m-quickstart"
9-
version = "0.2.6"
9+
version = "0.2.7"
1010

1111
[dependencies]
1212
cortex-m = "0.4.0"
13+
cortex-m-rt = "0.4.0"
1314
cortex-m-semihosting = "0.2.0"
14-
# alloc-cortex-m release doesn't use linked_list_allocator v0.5.0 yet.
15+
panic-abort = "0.1.1"
16+
panic-semihosting = "0.1.0"
1517
# Uncomment for the allocator example.
16-
#alloc-cortex-m = "0.3.2"
17-
18-
[dependencies.cortex-m-rt]
19-
version = "0.3.15"
20-
# Comment for the panic example.
21-
features = ["abort-on-panic"]
18+
#alloc-cortex-m = "0.3.3"
2219

2320
# Uncomment for the device example.
2421
# [dependencies.stm32f103xx]
2522
# features = ["rt"]
26-
# version = "0.8.0"
23+
# version = "0.9.0"
2724

2825
[profile.release]
2926
debug = true
3027
lto = true
28+
opt-level = "s"

LICENSE-MIT

+1-1
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@@ -1,4 +1,4 @@
1-
Copyright (c) 2017 {{toml-escape author}}
1+
Copyright (c) 2018
22

33
Permission is hereby granted, free of charge, to any
44
person obtaining a copy of this software and associated

bors.toml

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1+
status = [
2+
"continuous-integration/travis-ci/push",
3+
]

ci/install.sh

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@@ -0,0 +1,7 @@
1+
set -euxo pipefail
2+
3+
main() {
4+
rustup target add $TARGET
5+
}
6+
7+
main

ci/script.sh

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@@ -0,0 +1,72 @@
1+
set -euxo pipefail
2+
3+
main() {
4+
local td=$(mktemp -d)
5+
6+
git clone . $td
7+
pushd $td
8+
9+
cat >memory.x <<'EOF'
10+
MEMORY
11+
{
12+
/* NOTE K = KiBi = 1024 bytes */
13+
FLASH : ORIGIN = 0x08000000, LENGTH = 256K
14+
RAM : ORIGIN = 0x20000000, LENGTH = 40K
15+
}
16+
EOF
17+
18+
local examples=(
19+
crash
20+
hello
21+
override-exception-handler
22+
panic
23+
)
24+
for ex in "${examples[@]}"; do
25+
cargo build --target $TARGET --example $ex
26+
cargo build --target $TARGET --example $ex --release
27+
done
28+
29+
# ITM is not available on Cortex-M0
30+
if [ $TARGET != thumbv6m-none-eabi ]; then
31+
local ex=itm
32+
cargo build --target $TARGET --example $ex
33+
cargo build --target $TARGET --example $ex --release
34+
35+
examples+=( $ex )
36+
37+
fi
38+
39+
# Allocator example needs an extra dependency
40+
cat >>Cargo.toml <<'EOF'
41+
[dependencies.alloc-cortex-m]
42+
version = "0.3.3"
43+
EOF
44+
45+
local ex=allocator
46+
cargo build --target $TARGET --example $ex
47+
cargo build --target $TARGET --example $ex --release
48+
49+
examples+=( $ex )
50+
51+
# Device example needs an extra dependency
52+
if [ $TARGET = thumbv7m-none-eabi ]; then
53+
cat >>Cargo.toml <<'EOF'
54+
[dependencies.stm32f103xx]
55+
features = ["rt"]
56+
version = "0.9.0"
57+
EOF
58+
59+
local ex=device
60+
cargo build --target $TARGET --example $ex
61+
cargo build --target $TARGET --example $ex --release
62+
63+
examples+=( $ex )
64+
fi
65+
66+
IFS=,;eval arm-none-eabi-size target/$TARGET/release/examples/"{${examples[*]}}"
67+
68+
popd
69+
rm -rf $td
70+
}
71+
72+
main

examples/allocator.rs

+7-7
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@@ -1,7 +1,6 @@
11
//! How to use the heap and a dynamic memory allocator
22
//!
3-
//! This example depends on the alloc-cortex-m crate so you'll have to add it
4-
//! to your Cargo.toml:
3+
//! This example depends on the alloc-cortex-m crate so you'll have to add it to your Cargo.toml:
54
//!
65
//! ``` text
76
//! # or edit the Cargo.toml file manually
@@ -11,8 +10,8 @@
1110
//! ---
1211
1312
#![feature(alloc)]
14-
#![feature(used)]
1513
#![feature(global_allocator)]
14+
#![feature(used)]
1615
#![no_std]
1716

1817
// This is the allocator crate; you can use a different one
@@ -22,26 +21,27 @@ extern crate alloc;
2221
extern crate cortex_m;
2322
extern crate cortex_m_rt;
2423
extern crate cortex_m_semihosting;
24+
extern crate panic_abort; // panicking behavior
2525

2626
use core::fmt::Write;
2727

28+
use alloc_cortex_m::CortexMHeap;
2829
use cortex_m::asm;
2930
use cortex_m_semihosting::hio;
30-
use alloc_cortex_m::CortexMHeap;
3131

3232
#[global_allocator]
3333
static ALLOCATOR: CortexMHeap = CortexMHeap::empty();
3434

3535
extern "C" {
3636
static mut _sheap: u32;
37-
static mut _eheap: u32;
3837
}
3938

39+
const HEAP_SIZE: usize = 1024; // in bytes
40+
4041
fn main() {
4142
// Initialize the allocator
4243
let start = unsafe { &mut _sheap as *mut u32 as usize };
43-
let end = unsafe { &mut _eheap as *mut u32 as usize };
44-
unsafe { ALLOCATOR.init(start, end - start) }
44+
unsafe { ALLOCATOR.init(start, HEAP_SIZE) }
4545

4646
// Growable array allocated on the heap
4747
let xs = vec![0, 1, 2];

examples/crash.rs

+6-6
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,11 @@
11
//! Debugging a crash (exception)
22
//!
3-
//! The `cortex-m-rt` crate provides functionality for this through a default
4-
//! exception handler. When an exception is hit, the default handler will
5-
//! trigger a breakpoint and in this debugging context the stacked registers
6-
//! are accessible.
3+
//! The `cortex-m-rt` crate provides functionality for this through a default exception handler.
4+
//! When an exception is hit, the default handler will trigger a breakpoint and in this debugging
5+
//! context the stacked registers are accessible.
76
//!
8-
//! In you run the example below, you'll be able to inspect the state of your
9-
//! program under the debugger using these commands:
7+
//! In you run the example below, you'll be able to inspect the state of your program under the
8+
//! debugger using these commands:
109
//!
1110
//! ``` text
1211
//! (gdb) # Exception frame = program state during the crash
@@ -63,6 +62,7 @@
6362

6463
extern crate cortex_m;
6564
extern crate cortex_m_rt;
65+
extern crate panic_abort; // panicking behavior
6666

6767
use core::ptr;
6868

examples/device.rs

+11-14
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,22 @@
11
//! Using a device crate
22
//!
3-
//! Crates generated using [`svd2rust`] are referred to as device crates. These
4-
//! crates provides an API to access the peripherals of a device. When you
5-
//! depend on one of these crates and the "rt" feature is enabled you don't need
6-
//! link to the cortex-m-rt crate.
3+
//! Crates generated using [`svd2rust`] are referred to as device crates. These crates provides an
4+
//! API to access the peripherals of a device. When you depend on one of these crates and the "rt"
5+
//! feature is enabled you don't need link to the cortex-m-rt crate.
76
//!
87
//! [`svd2rust`]: https://crates.io/crates/svd2rust
98
//!
10-
//! Device crates also provide an `interrupt!` macro to register interrupt
11-
//! handlers.
9+
//! Device crates also provide an `interrupt!` macro to register interrupt handlers.
1210
//!
13-
//! This example depends on the [`stm32f103xx`] crate so you'll have to add it
14-
//! to your Cargo.toml.
11+
//! This example depends on the [`stm32f103xx`] crate so you'll have to add it to your Cargo.toml.
1512
//!
1613
//! [`stm32f103xx`]: https://crates.io/crates/stm32f103xx
1714
//!
1815
//! ```
19-
//! $ edit Cargo.toml && cat $_
16+
//! $ edit Cargo.toml && tail $_
2017
//! [dependencies.stm32f103xx]
2118
//! features = ["rt"]
22-
//! version = "0.8.0"
19+
//! version = "0.9.0"
2320
//! ```
2421
//!
2522
//! ---
@@ -29,9 +26,11 @@
2926
#![no_std]
3027

3128
extern crate cortex_m;
29+
// extern crate cortex_m_rt; // included in the device crate
3230
extern crate cortex_m_semihosting;
3331
#[macro_use(exception, interrupt)]
3432
extern crate stm32f103xx;
33+
extern crate panic_abort; // panicking behavior
3534

3635
use core::cell::RefCell;
3736
use core::fmt::Write;
@@ -41,11 +40,9 @@ use cortex_m::peripheral::syst::SystClkSource;
4140
use cortex_m_semihosting::hio::{self, HStdout};
4241
use stm32f103xx::Interrupt;
4342

44-
static HSTDOUT: Mutex<RefCell<Option<HStdout>>> =
45-
Mutex::new(RefCell::new(None));
43+
static HSTDOUT: Mutex<RefCell<Option<HStdout>>> = Mutex::new(RefCell::new(None));
4644

47-
static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> =
48-
Mutex::new(RefCell::new(None));
45+
static NVIC: Mutex<RefCell<Option<cortex_m::peripheral::NVIC>>> = Mutex::new(RefCell::new(None));
4946

5047
fn main() {
5148
let global_p = cortex_m::Peripherals::take().unwrap();

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