Update to Rust 2018

Author: andre-richter

.gitignore

@@ -1 +1,2 @@
+target
 Cargo.lock

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "cortex-a"
-version = "2.2.2"
+version = "2.3.1"
 authors = ["Andre Richter <[email protected]>"]
 description = "Low level access to Cortex-A processors"
 homepage = "https://github.com/rust-embedded/cortex-a"
@@ -9,9 +9,11 @@ readme = "README.md"
 keywords = ["arm", "aarch64", "cortex-a", "register"]
 categories = ["embedded", "hardware-support", "no-std"]
 license = "MIT/Apache-2.0"
+edition = "2018"
 exclude = [
-    "Makefile",
+        ".gitignore",
+        "Makefile",
 ]
 
 [dependencies]
-register = "0.2.0"
+register = "0.3.2"

Makefile

@@ -6,5 +6,12 @@ default:
 clippy:
 	cargo xclippy --target $(TARGET)
 
+fmt:
+	cargo fmt
+
+ready: clippy fmt
+	git pull
+	cargo package --allow-dirty
+
 clean:
 	cargo clean

README.md

@@ -7,11 +7,9 @@ Low level access to Cortex-A processors
 
 ## Usage
 
-Example from https://github.com/andre-richter/rust-raspi3-tutorial
+Example from https://github.com/rust-embedded/rust-raspi3-tutorial
 
 ```rust
-extern crate cortex_a;
-
 #[no_mangle]
 pub unsafe extern "C" fn _boot_cores() -> ! {
     use cortex_a::{asm, regs::*};

src/lib.rs

@@ -11,9 +11,6 @@
 #![no_std]
 #![feature(core_intrinsics)]
 
-#[macro_use]
-extern crate register;
-
 pub mod asm;
 pub mod barrier;
 pub mod regs;

src/regs/cnthctl_el2.rs

@@ -20,7 +20,7 @@
 //! access from Non-secure EL1 to the physical counter and the Non-secure EL1
 //! physical timer.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 // When HCR_EL2.E2H == 0:
 // TODO: Figure out how we can differentiate depending on HCR_EL2.E2H state

src/regs/cntp_ctl_el0.rs

@@ -18,7 +18,7 @@
 //!
 //! Control register for the EL1 physical timer.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 register_bitfields! {u32,
     CNTP_CTL_EL0 [

src/regs/currentel.rs

@@ -18,7 +18,7 @@
 //!
 //! Holds the current Exception level.
 
-use register::cpu::RegisterReadOnly;
+use register::{cpu::RegisterReadOnly, register_bitfields};
 
 register_bitfields! {u32,
     CurrentEL [

src/regs/daif.rs

@@ -18,7 +18,7 @@
 //!
 //! Allows access to the interrupt mask bits.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 register_bitfields! {u32,
     DAIF [
@@ -79,7 +79,6 @@ register_bitfields! {u32,
     ]
 }
 
-
 pub struct Reg;
 
 impl RegisterReadWrite<u32, DAIF::Register> for Reg {

src/regs/hcr_el2.rs

@@ -19,7 +19,7 @@
 //! Provides configuration controls for virtualization, including defining
 //! whether various Non-secure operations are trapped to EL2.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 register_bitfields! {u64,
     HCR_EL2 [

src/regs/id_aa64mmfr0_el1.rs

@@ -19,7 +19,7 @@
 //! Provides information about the implemented memory model and memory
 //! management support in AArch64 state.
 
-use register::cpu::RegisterReadOnly;
+use register::{cpu::RegisterReadOnly, register_bitfields};
 
 register_bitfields! {u64,
     ID_AA64MMFR0_EL1 [

src/regs/mair_el1.rs

@@ -20,7 +20,7 @@
 //! AttrIndx values in a Long-descriptor format translation table entry for
 //! stage 1 translations at EL1.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 register_bitfields! {u64,
     MAIR_EL1 [

src/regs/sctlr_el1.rs

@@ -19,7 +19,7 @@
 //! Provides top level control of the system, including its memory system, at
 //! EL1 and EL0.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 register_bitfields! {u32,
     SCTLR_EL1 [

src/regs/spsel.rs

@@ -18,7 +18,7 @@
 //!
 //! Allows the Stack Pointer to be selected between SP_EL0 and SP_ELx.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 register_bitfields! {u32,
     SPSel [
@@ -36,7 +36,6 @@ register_bitfields! {u32,
     ]
 }
 
-
 pub struct Reg;
 
 impl RegisterReadWrite<u32, SPSel::Register> for Reg {

src/regs/spsr_el2.rs

@@ -18,7 +18,7 @@
 //!
 //! Holds the saved process state when an exception is taken to EL2.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 register_bitfields! {u32,
     SPSR_EL2 [

src/regs/tcr_el1.rs

@@ -18,7 +18,7 @@
 //!
 //! The control register for stage 1 of the EL1&0 translation regime.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 register_bitfields! {u64,
     TCR_EL1 [

src/regs/ttbr0_el1.rs

@@ -20,7 +20,7 @@
 //! stage 1 of the translation of an address from the lower VA range in the
 //! EL1&0 translation regime, and other information for this translation regime.
 
-use register::cpu::RegisterReadWrite;
+use register::{cpu::RegisterReadWrite, register_bitfields};
 
 register_bitfields! {u64,
     TTBR0_EL1 [