Add first draft ethernet support

Author: dtwood

tm4c129x-hal/Cargo.toml

@@ -15,10 +15,15 @@ repository = "https://github.com/thejpster/tm4c-hal/tm4c129x-hal"
 edition = "2018"
 
 [dependencies]
+bare-metal = "*"
 cortex-m = "0.5"
 nb = "0.1"
 tm4c129x = "0.7"
 
+[dependencies.byteorder]
+version = "1"
+default-features = false
+
 [dependencies.cast]
 version = "0.2"
 default-features = false
@@ -27,6 +32,17 @@ default-features = false
 version = "0.2"
 features = ["unproven"]
 
+[dependencies.smoltcp]
+git = "https://github.com/m-labs/smoltcp"
+default_features = false
+features = [
+    "proto-ipv4",
+    "proto-ipv6",
+    "socket-raw",
+    "socket-udp",
+    "socket-tcp",
+]
+
 [dependencies.void]
 version = "1.0"
 default-features = false
@@ -35,5 +51,9 @@ default-features = false
 # path = "../tm4c-hal"
 version = "0.2.2"
 
+[dependencies.vcell]
+version = "*"
+features = ["const-fn"]
+
 [features]
 rt = ["tm4c129x/rt"]

tm4c129x-hal/src/edes.rs

@@ -0,0 +1,99 @@
+pub const DES0_TX_CTRL_OWN: u32 = 2147483648;
+pub const DES0_TX_CTRL_INTERRUPT: u32 = 1073741824;
+pub const DES0_TX_CTRL_LAST_SEG: u32 = 536870912;
+pub const DES0_TX_CTRL_FIRST_SEG: u32 = 268435456;
+pub const DES0_TX_CTRL_DISABLE_CRC: u32 = 134217728;
+pub const DES0_TX_CTRL_DISABLE_PADDING: u32 = 67108864;
+pub const DES0_TX_CTRL_ENABLE_TS: u32 = 33554432;
+pub const DES0_TX_CTRL_REPLACE_CRC: u32 = 16777216;
+pub const DES0_TX_CTRL_CHKSUM_M: u32 = 12582912;
+pub const DES0_TX_CTRL_NO_CHKSUM: u32 = 0;
+pub const DES0_TX_CTRL_IP_HDR_CHKSUM: u32 = 4194304;
+pub const DES0_TX_CTRL_IP_HDR_PAY_CHKSUM: u32 = 8388608;
+pub const DES0_TX_CTRL_IP_ALL_CKHSUMS: u32 = 12582912;
+pub const DES0_TX_CTRL_END_OF_RING: u32 = 2097152;
+pub const DES0_TX_CTRL_CHAINED: u32 = 1048576;
+pub const DES0_TX_CTRL_VLAN_M: u32 = 786432;
+pub const DES0_TX_CTRL_VLAN_NONE: u32 = 0;
+pub const DES0_TX_CTRL_VLAN_REMOVE: u32 = 262144;
+pub const DES0_TX_CTRL_VLAN_INSERT: u32 = 524288;
+pub const DES0_TX_CTRL_VLAN_REPLACE: u32 = 786432;
+pub const DES0_TX_STAT_TS_CAPTURED: u32 = 131072;
+pub const DES0_TX_STAT_IPH_ERR: u32 = 65536;
+pub const DES0_TX_STAT_ERR: u32 = 32768;
+pub const DES0_TX_STAT_JABBER_TO: u32 = 16384;
+pub const DES0_TX_STAT_FLUSHED: u32 = 8192;
+pub const DES0_TX_STAT_PAYLOAD_ERR: u32 = 4096;
+pub const DES0_TX_STAT_CARRIER_LOST: u32 = 2048;
+pub const DES0_TX_STAT_NO_CARRIER: u32 = 1024;
+pub const DES0_TX_STAT_TX_L_COLLISION: u32 = 512;
+pub const DES0_TX_STAT_E_COLLISION: u32 = 256;
+pub const DES0_TX_STAT_VLAN_FRAME: u32 = 128;
+pub const DES0_TX_STAT_COL_COUNT_M: u32 = 120;
+pub const DES0_TX_STAT_COL_COUNT_S: u32 = 3;
+pub const DES0_TX_STAT_E_DEFERRAL: u32 = 4;
+pub const DES0_TX_STAT_UNDERFLOW: u32 = 2;
+pub const DES0_TX_STAT_DEFERRED: u32 = 1;
+pub const DES1_TX_CTRL_SADDR_MAC1: u32 = 2147483648;
+pub const DES1_TX_CTRL_SADDR_M: u32 = 1610612736;
+pub const DES1_TX_CTRL_SADDR_NONE: u32 = 0;
+pub const DES1_TX_CTRL_SADDR_INSERT: u32 = 536870912;
+pub const DES1_TX_CTRL_SADDR_REPLACE: u32 = 1073741824;
+pub const DES1_TX_CTRL_BUFF2_SIZE_M: u32 = 536805376;
+pub const DES1_TX_CTRL_BUFF1_SIZE_M: u32 = 8191;
+pub const DES1_TX_CTRL_BUFF2_SIZE_S: u32 = 16;
+pub const DES1_TX_CTRL_BUFF1_SIZE_S: u32 = 0;
+pub const DES0_RX_CTRL_OWN: u32 = 2147483648;
+pub const DES0_RX_STAT_DEST_ADDR_FAIL: u32 = 1073741824;
+pub const DES0_RX_STAT_FRAME_LENGTH_M: u32 = 1073676288;
+pub const DES0_RX_STAT_FRAME_LENGTH_S: u32 = 16;
+pub const DES0_RX_STAT_ERR: u32 = 32768;
+pub const DES0_RX_STAT_DESCRIPTOR_ERR: u32 = 16384;
+pub const DES0_RX_STAT_SRC_ADDR_FAIL: u32 = 8192;
+pub const DES0_RX_STAT_LENGTH_ERR: u32 = 4096;
+pub const DES0_RX_STAT_OVERFLOW: u32 = 2048;
+pub const DES0_RX_STAT_VLAN_TAG: u32 = 1024;
+pub const DES0_RX_STAT_FIRST_DESC: u32 = 512;
+pub const DES0_RX_STAT_LAST_DESC: u32 = 256;
+pub const DES0_RX_STAT_TS_AVAILABLE: u32 = 128;
+pub const DES0_RX_STAT_RX_L_COLLISION: u32 = 64;
+pub const DES0_RX_STAT_FRAME_TYPE: u32 = 32;
+pub const DES0_RX_STAT_WDOG_TIMEOUT: u32 = 16;
+pub const DES0_RX_STAT_RX_ERR: u32 = 8;
+pub const DES0_RX_STAT_DRIBBLE_ERR: u32 = 4;
+pub const DES0_RX_STAT_CRC_ERR: u32 = 2;
+pub const DES0_RX_STAT_MAC_ADDR: u32 = 1;
+pub const DES0_RX_STAT_EXT_AVAILABLE: u32 = 1;
+pub const DES1_RX_CTRL_DISABLE_INT: u32 = 2147483648;
+pub const DES1_RX_CTRL_BUFF2_SIZE_M: u32 = 536805376;
+pub const DES1_RX_CTRL_BUFF2_SIZE_S: u32 = 16;
+pub const DES1_RX_CTRL_END_OF_RING: u32 = 32768;
+pub const DES1_RX_CTRL_CHAINED: u32 = 16384;
+pub const DES1_RX_CTRL_BUFF1_SIZE_M: u32 = 8191;
+pub const DES1_RX_CTRL_BUFF1_SIZE_S: u32 = 0;
+pub const DES4_RX_STAT_TS_DROPPED: u32 = 16384;
+pub const DES4_RX_STAT_PTP_VERSION2: u32 = 8192;
+pub const DES4_RX_STAT_PTP_TYPE_ETH: u32 = 4096;
+pub const DES4_RX_STAT_PTP_TYPE_UDP: u32 = 0;
+pub const DES4_RX_STAT_PTP_MT_M: u32 = 3840;
+pub const DES4_RX_STAT_PTP_MT_NONE: u32 = 0;
+pub const DES4_RX_STAT_PTP_MT_SYNC: u32 = 256;
+pub const DES4_RX_STAT_PTP_MT_FOLLOW_UP: u32 = 512;
+pub const DES4_RX_STAT_PTP_MT_DELAY_REQ: u32 = 768;
+pub const DES4_RX_STAT_PTP_MT_DELAY_RESP: u32 = 1024;
+pub const DES4_RX_STAT_PTP_MT_PDELAY_REQ: u32 = 1280;
+pub const DES4_RX_STAT_PTP_MT_PDELAY_RESP: u32 = 1536;
+pub const DES4_RX_STAT_PTP_MT_PDELAY_RFU: u32 = 1792;
+pub const DES4_RX_STAT_PTP_MT_ANNOUNCE: u32 = 2048;
+pub const DES4_RX_STAT_PTP_MT_SIGNALLING: u32 = 2560;
+pub const DES4_RX_STAT_PTP_MT_RESERVED: u32 = 3840;
+pub const DES4_RX_STAT_IPV6: u32 = 128;
+pub const DES4_RX_STAT_IPV4: u32 = 64;
+pub const DES4_RX_STAT_IP_CHK_BYPASSED: u32 = 32;
+pub const DES4_RX_STAT_IP_PAYLOAD_ERR: u32 = 16;
+pub const DES4_RX_STAT_IP_HEADER_ERR: u32 = 8;
+pub const DES4_RX_STAT_PAYLOAD_M: u32 = 7;
+pub const DES4_RX_STAT_PAYLOAD_UNKNOWN: u32 = 0;
+pub const DES4_RX_STAT_PAYLOAD_UDP: u32 = 1;
+pub const DES4_RX_STAT_PAYLOAD_TCP: u32 = 2;
+pub const DES4_RX_STAT_PAYLOAD_ICMP: u32 = 3;