fix: migrate to 2024 edition and fmt

Ddystopia · Ddystopia · commit c0920e58fab6 · 2025-05-15T16:49:10.000+02:00
diff --git a/rtic/src/export/cortex_basepri.rs b/rtic/src/export/cortex_basepri.rs
@@ -1,10 +1,10 @@
 use super::cortex_logical2hw;
 use cortex_m::register::{basepri, basepri_max};
 pub use cortex_m::{
+    Peripherals,
     asm::wfi,
     interrupt,
-    peripheral::{scb::SystemHandler, DWT, SCB, SYST},
-    Peripherals,
+    peripheral::{DWT, SCB, SYST, scb::SystemHandler},
 };
 
 #[cfg(not(any(feature = "thumbv7-backend", feature = "thumbv8main-backend")))]
@@ -69,13 +69,15 @@ pub unsafe fn lock<T, R>(
     nvic_prio_bits: u8,
     f: impl FnOnce(&mut T) -> R,
 ) -> R {
-    if ceiling == (1 << nvic_prio_bits) {
-        critical_section::with(|_| f(&mut *ptr))
-    } else {
-        let current = basepri::read();
-        basepri_max::write(cortex_logical2hw(ceiling, nvic_prio_bits));
-        let r = f(&mut *ptr);
-        basepri::write(current);
-        r
+    unsafe {
+        if ceiling == (1 << nvic_prio_bits) {
+            critical_section::with(|_| f(&mut *ptr))
+        } else {
+            let current = basepri::read();
+            basepri_max::write(cortex_logical2hw(ceiling, nvic_prio_bits));
+            let r = f(&mut *ptr);
+            basepri::write(current);
+            r
+        }
     }
 }
diff --git a/rtic/src/export/cortex_source_mask.rs b/rtic/src/export/cortex_source_mask.rs
@@ -1,8 +1,8 @@
 pub use cortex_m::{
+    Peripherals,
     asm::wfi,
     interrupt,
-    peripheral::{scb::SystemHandler, DWT, NVIC, SCB, SYST},
-    Peripherals,
+    peripheral::{DWT, NVIC, SCB, SYST, scb::SystemHandler},
 };
 
 #[cfg(not(any(feature = "thumbv6-backend", feature = "thumbv8base-backend")))]
@@ -57,7 +57,9 @@ impl<const M: usize> Mask<M> {
         let block = bit / 32;
 
         if block as usize >= M {
-            panic!("Generating masks for thumbv6/thumbv8m.base failed! Are you compiling for thumbv6 on an thumbv7 MCU or using an unsupported thumbv8m.base MCU?");
+            panic!(
+                "Generating masks for thumbv6/thumbv8m.base failed! Are you compiling for thumbv6 on an thumbv7 MCU or using an unsupported thumbv8m.base MCU?"
+            );
         }
 
         let offset = bit - (block * 32);
diff --git a/rtic/src/export/executor.rs b/rtic/src/export/executor.rs
@@ -17,7 +17,7 @@ unsafe fn waker_clone(p: *const ()) -> RawWaker {
 unsafe fn waker_wake(p: *const ()) {
     // The only thing we need from a waker is the function to call to pend the async
     // dispatcher.
-    let f: fn() = mem::transmute(p);
+    let f: fn() = unsafe { mem::transmute(p) };
     f();
 }
 
@@ -81,7 +81,7 @@ macro_rules! from_ptr_n_args {
     ($name:ident, $($t:ident),*) => {
         #[inline(always)]
         pub unsafe fn $name<$($t,)* Fun: Fn($($t,)*) -> F>(_f: Fun, ptr: &AsyncTaskExecutorPtr) -> &Self {
-            &*(ptr.get() as *const _)
+            unsafe { &*(ptr.get() as *const _) }
         }
     };
 }
diff --git a/rtic/src/export/riscv_esp32c3.rs b/rtic/src/export/riscv_esp32c3.rs
@@ -10,26 +10,24 @@ pub fn run<F>(priority: u8, f: F)
 where
     F: FnOnce(),
 {
-    if priority == 1 {
-        //if priority is 1, priority thresh should be 1
-        f();
-        unsafe {
+    unsafe {
+        if priority == 1 {
+            //if priority is 1, priority thresh should be 1
+            f();
+
             (*INTERRUPT_CORE0::ptr())
                 .cpu_int_thresh()
                 .write(|w| w.cpu_int_thresh().bits(1));
-        }
-    } else {
-        //read current thresh
-        let initial = unsafe {
-            (*INTERRUPT_CORE0::ptr())
+        } else {
+            //read current thresh
+            let initial = (*INTERRUPT_CORE0::ptr())
                 .cpu_int_thresh()
                 .read()
                 .cpu_int_thresh()
-                .bits()
-        };
-        f();
-        //write back old thresh
-        unsafe {
+                .bits();
+            f();
+            //write back old thresh
+
             (*INTERRUPT_CORE0::ptr())
                 .cpu_int_thresh()
                 .write(|w| w.cpu_int_thresh().bits(initial));
@@ -55,30 +53,29 @@ where
 /// priority is current priority >= ceiling.
 #[inline(always)]
 pub unsafe fn lock<T, R>(ptr: *mut T, ceiling: u8, f: impl FnOnce(&mut T) -> R) -> R {
-    if ceiling == (15) {
-        //turn off interrupts completely, were at max prio
-        critical_section::with(|_| f(&mut *ptr))
-    } else {
-        let current = unsafe {
-            (*INTERRUPT_CORE0::ptr())
+    unsafe {
+        if ceiling == (15) {
+            //turn off interrupts completely, were at max prio
+            critical_section::with(|_| f(&mut *ptr))
+        } else {
+            let current = (*INTERRUPT_CORE0::ptr())
                 .cpu_int_thresh()
                 .read()
                 .cpu_int_thresh()
-                .bits()
-        };
+                .bits();
 
-        unsafe {
             (*INTERRUPT_CORE0::ptr())
                 .cpu_int_thresh()
                 .write(|w| w.cpu_int_thresh().bits(ceiling + 1));
-        } //esp32c3 lets interrupts with prio equal to threshold through so we up it by one
-        let r = f(&mut *ptr);
-        unsafe {
+            //esp32c3 lets interrupts with prio equal to threshold through so we up it by one
+            let r = f(&mut *ptr);
+
             (*INTERRUPT_CORE0::ptr())
                 .cpu_int_thresh()
                 .write(|w| w.cpu_int_thresh().bits(current));
+
+            r
         }
-        r
     }
 }
 
diff --git a/rtic/src/export/riscv_esp32c6.rs b/rtic/src/export/riscv_esp32c6.rs
@@ -1,5 +1,5 @@
-pub use esp32c6::{Interrupt, Peripherals};
 use esp32c6::{INTERRUPT_CORE0, PLIC_MX};
+pub use esp32c6::{Interrupt, Peripherals};
 pub use riscv::interrupt;
 pub use riscv::register::mcause;
 
@@ -11,26 +11,24 @@ pub fn run<F>(priority: u8, f: F)
 where
     F: FnOnce(),
 {
-    if priority == 1 {
-        //if priority is 1, priority thresh should be 1
-        f();
-        unsafe {
+    unsafe {
+        if priority == 1 {
+            //if priority is 1, priority thresh should be 1
+            f();
+
             (*PLIC_MX::ptr())
                 .mxint_thresh()
                 .write(|w| w.cpu_mxint_thresh().bits(1));
-        }
-    } else {
-        //read current thresh
-        let initial = unsafe {
-            (*PLIC_MX::ptr())
+        } else {
+            //read current thresh
+            let initial = (*PLIC_MX::ptr())
                 .mxint_thresh()
                 .read()
                 .cpu_mxint_thresh()
-                .bits()
-        };
-        f();
-        //write back old thresh
-        unsafe {
+                .bits();
+            f();
+            //write back old thresh
+
             (*PLIC_MX::ptr())
                 .mxint_thresh()
                 .write(|w| w.cpu_mxint_thresh().bits(initial));
@@ -56,34 +54,30 @@ where
 /// priority is current priority >= ceiling.
 #[inline(always)]
 pub unsafe fn lock<T, R>(ptr: *mut T, ceiling: u8, f: impl FnOnce(&mut T) -> R) -> R {
-    if ceiling == (15) {
-        // Turn off interrupts completely, we're at max prio
-        critical_section::with(|_| f(&mut *ptr))
-    } else {
-        let current = unsafe {
-            (*PLIC_MX::ptr())
+    unsafe {
+        if ceiling == (15) {
+            // Turn off interrupts completely, we're at max prio
+            critical_section::with(|_| f(&mut *ptr))
+        } else {
+            let current = (*PLIC_MX::ptr())
                 .mxint_thresh()
                 .read()
                 .cpu_mxint_thresh()
-                .bits()
-        };
+                .bits();
 
-        // esp32c6 lets interrupts with prio equal to threshold through so we up it by one
-        unsafe {
+            // esp32c6 lets interrupts with prio equal to threshold through so we up it by one
             (*PLIC_MX::ptr())
                 .mxint_thresh()
                 .write(|w| w.cpu_mxint_thresh().bits(ceiling + 1));
-        }
 
-        let r = f(&mut *ptr);
+            let r = f(&mut *ptr);
 
-        unsafe {
             (*PLIC_MX::ptr())
                 .mxint_thresh()
                 .write(|w| w.cpu_mxint_thresh().bits(current));
-        }
 
-        r
+            r
+        }
     }
 }
 
diff --git a/rtic/src/export/slic.rs b/rtic/src/export/slic.rs
@@ -1,4 +1,4 @@
-pub use riscv_slic::{lock, pend, run, InterruptNumber};
+pub use riscv_slic::{InterruptNumber, lock, pend, run};
 
 #[cfg(all(
     feature = "riscv-slic",
diff --git a/rtic/src/lib.rs b/rtic/src/lib.rs
@@ -33,13 +33,13 @@
 #![allow(clippy::inline_always)]
 #![allow(unexpected_cfgs)]
 
-pub use rtic_core::{prelude as mutex_prelude, Exclusive, Mutex};
+pub use rtic_core::{Exclusive, Mutex, prelude as mutex_prelude};
 pub use rtic_macros::app;
 
 /// module `mutex::prelude` provides `Mutex` and multi-lock variants. Recommended over `mutex_prelude`
 pub mod mutex {
-    pub use rtic_core::prelude;
     pub use rtic_core::Mutex;
+    pub use rtic_core::prelude;
 }
 
 #[doc(hidden)]

Original file line number	Diff line number	Diff line change
`@@ -17,7 +17,7 @@ unsafe fn waker_clone(p: *const ()) -> RawWaker {`
`17`	`17`	`unsafe fn waker_wake(p: *const ()) {`
`18`	`18`	`// The only thing we need from a waker is the function to call to pend the async`
`19`	`19`	`// dispatcher.`
`20`		`- let f: fn() = mem::transmute(p);`
	`20`	`+ let f: fn() = unsafe { mem::transmute(p) };`
`21`	`21`	`f();`
`22`	`22`	`}`
`23`	`23`
`@@ -81,7 +81,7 @@ macro_rules! from_ptr_n_args {`
`81`	`81`	`($name:ident, $($t:ident),*) => {`
`82`	`82`	`#[inline(always)]`
`83`	`83`	`pub unsafe fn $name<$($t,)* Fun: Fn($($t,)*) -> F>(_f: Fun, ptr: &AsyncTaskExecutorPtr) -> &Self {`
`84`		`- &(ptr.get() as const _)`
	`84`	`+ unsafe { &(ptr.get() as const _) }`
`85`	`85`	`}`
`86`	`86`	`};`
`87`	`87`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-pub use riscv_slic::{lock, pend, run, InterruptNumber};`
	`1`	`+pub use riscv_slic::{InterruptNumber, lock, pend, run};`
`2`	`2`
`3`	`3`	`#[cfg(all(`
`4`	`4`	`feature = "riscv-slic",`