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rtic: placate clippy for esp32c3
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+27
-56
lines changed

5 files changed

+27
-56
lines changed

.github/workflows/build.yml

Lines changed: 0 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -74,53 +74,6 @@ jobs:
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platform: esp32-c3
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rustup-target: riscv32imc-unknown-none-elf
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# Clippy
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# TODO: put in clippy-check-example once esp32-c3 clippy is fixed
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clippy:
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name: clippy
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runs-on: ubuntu-22.04
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strategy:
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matrix:
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input:
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- backend: thumbv7
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platform: lm3s6965
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rustup-target: thumbv7m-none-eabi
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- backend: thumbv6
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platform: lm3s6965
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rustup-target: thumbv6m-none-eabi
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- backend: thumbv8-base
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platform: lm3s6965
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rustup-target: thumbv8m.base-none-eabi
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- backend: thumbv8-main
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platform: lm3s6965
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rustup-target: thumbv8m.main-none-eabi
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- backend: riscv32-imc-clint
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platform: hifive1
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rustup-target: riscv32imc-unknown-none-elf
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- backend: riscv32-imc-mecall
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platform: hifive1
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rustup-target: riscv32imc-unknown-none-elf
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steps:
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- name: Checkout
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uses: actions/checkout@v4
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- name: Configure Rust target ${{ matrix.input.rustup-target }}
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run: rustup target add ${{ matrix.input.rustup-target }}
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- name: Add Rust component clippy
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run: rustup component add clippy
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- name: Cache Dependencies
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uses: Swatinem/rust-cache@v2
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- run: cargo xtask --deny-warnings --platform ${{ matrix.input.platform }} --backend ${{ matrix.input.backend }} clippy
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buildqemu:
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name: Get modern QEMU, build and store
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runs-on: ubuntu-22.04

.github/workflows/clippy-check-example.yml

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,4 +53,22 @@ jobs:
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uses: Swatinem/rust-cache@v2
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- name: Check the examples
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run: cargo xtask example-check --platform ${{ inputs.platform }} --backend ${{ inputs.backend }} ${{ inputs.example-args }}
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run: cargo xtask example-check --platform ${{ inputs.platform }} --backend ${{ inputs.backend }} ${{ inputs.example-args }}
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clippy:
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runs-on: ubuntu-22.04
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name: Run clippy
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steps:
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- name: Checkout
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uses: actions/checkout@v4
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- name: Configure Rust target ${{ inputs.rustup-target }}
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run: rustup target add ${{ inputs.rustup-target }}
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- name: Add Rust component clippy
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run: rustup component add clippy
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- name: Cache Dependencies
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uses: Swatinem/rust-cache@v2
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- run: cargo xtask --deny-warnings --platform ${{ inputs.platform }} --backend ${{ inputs.backend }} clippy

rtic-macros/src/codegen/bindings/esp32c3.rs

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
pub use esp32c3::*;
33

44
#[cfg(feature = "riscv-esp32c3")]
5+
#[allow(clippy::module_inception)]
56
mod esp32c3 {
67
use crate::{
78
analyze::Analysis as CodegenAnalysis,
@@ -92,7 +93,7 @@ mod esp32c3 {
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for (&priority, name) in interrupt_ids.chain(
9394
app.hardware_tasks
9495
.values()
95-
.filter_map(|task| Some((&task.args.priority, &task.args.binds))),
96+
.map(|task| (&task.args.priority, &task.args.binds)),
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) {
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let es = format!(
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"Maximum priority used by interrupt vector '{name}' is more than supported by hardware"
@@ -207,7 +208,7 @@ mod esp32c3 {
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stmts
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}
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210-
pub fn async_prio_limit(app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
211+
pub fn async_prio_limit(_app: &App, analysis: &CodegenAnalysis) -> Vec<TokenStream2> {
211212
let max = if let Some(max) = analysis.max_async_prio {
212213
quote!(#max)
213214
} else {
@@ -232,7 +233,7 @@ mod esp32c3 {
232233
for (_, name) in interrupt_ids.chain(
233234
app.hardware_tasks
234235
.values()
235-
.filter_map(|task| Some((&task.args.priority, &task.args.binds))),
236+
.map(|task| (&task.args.priority, &task.args.binds)),
236237
) {
237238
if *name == dispatcher_name {
238239
let ret = &("interrupt".to_owned() + &curr_cpu_id.to_string());

rtic-monotonics/src/esp32c3.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,8 +49,8 @@ impl TimerBackend {
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/// Use the prelude macros instead.
5050
pub fn _start(timer: SYSTIMER) {
5151
const INTERRUPT_MAP_BASE: u32 = 0x600c2000;
52-
let interrupt_number = 37 as isize;
53-
let cpu_interrupt_number = 31 as isize;
52+
let interrupt_number = 37isize;
53+
let cpu_interrupt_number = 31isize;
5454
unsafe {
5555
let intr_map_base = INTERRUPT_MAP_BASE as *mut u32;
5656
intr_map_base
@@ -65,7 +65,7 @@ impl TimerBackend {
6565

6666
intr_prio_base
6767
.offset(cpu_interrupt_number)
68-
.write_volatile(15 as u32);
68+
.write_volatile(15);
6969
}
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timer.conf().write(|w| w.timer_unit0_work_en().set_bit());
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timer

rtic/src/export/riscv_esp32c3.rs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,7 @@ where
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pub unsafe fn lock<T, R>(ptr: *mut T, ceiling: u8, f: impl FnOnce(&mut T) -> R) -> R {
5858
if ceiling == (15) {
5959
//turn off interrupts completely, were at max prio
60-
let r = critical_section::with(|_| f(&mut *ptr));
61-
r
60+
critical_section::with(|_| f(&mut *ptr))
6261
} else {
6362
let current = unsafe {
6463
(*INTERRUPT_CORE0::ptr())

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