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RSD Wiki Home (English)

This is a wiki about RSD development.

Notice

• Most pages are under construction. We are now preparing them.
• We temporally provide auto-translated ones in many pages.
• Be sure to write the title at the top of each page first in the form of "# page title".
• Please create an English page under "en-".
  • Use "-" for grouping page names if needed.

Getting Started

Start from here

Pages

Development

• Getting started
• Development environment
• Environment variables
• List of directives
• Coding convention

Architecture

• Binary
• Microarchitecture

Test & Debugging

• How to compile and run your program on Verilator

FPGA

• How to run RSD on a Zynq board
• How to run post-synthesis simulation for FPGA

Currently, the following pages are generated by automatic translation

Development

• Repository update rules

Test & debugging

• Test programs
• Troubleshooting
• Unit test
• Coremark
• Comparison of execution results with QEMU
• Functional simulation
• Functional simulation by Verilator

Architecture

• Memory map

Synthesize

• Constraints
• Simulation using synthesis results
• Synthesis by Synplify
• How to Synthesis

FPGA (for synthesis for ZYNQ)

• Clock generator
• Memory controller
• System architecture
• Linux in PS section