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RSD Wiki Home (English)

This is a wiki about RSD development.

Notice

• Most pages are under construction. We are now preparing them.
• Be sure to write the title at the top of each page first in the form of "# page title".
• Please create an English page under "en-".
  • Use "-" for grouping page names if needed.

Getting Started

Start from here.

Pages

Development

• Getting started

Under construction

Development

• List of directives
• Coding convention
• Repository update rules

Environment

• Setup

Test & debugging

• Test programs
• Troubleshooting
• Unit test
• Coremark
• Comparison of execution results with QEMU
• Functional simulation by Verilator
• Functional simulation by Questa

Architecture

• Memory map
• Microarchitecture

Synthesize

• Constraints
• Simulation using synthesis results
• Synthesis by Synplify
• Synthesis by Vivado

FPGA (for synthesis for ZYNQ)

• Clock generator
• Memory controller
• System architecture
• Linux in PS section
• How to build Linux (details)
• How to build Linux (Simplified version)