@@ -623,12 +623,12 @@ static int find_first_trigger_by_id(struct target *target, int unique_id)
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static unsigned int count_trailing_ones (riscv_reg_t reg )
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{
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- assert ( sizeof (riscv_reg_t ) * 8 == 64 ) ;
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- for (unsigned int i = 0 ; i < 64 ; i ++ ) {
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+ const unsigned int riscv_reg_bits = sizeof (riscv_reg_t ) * CHAR_BIT ;
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+ for (unsigned int i = 0 ; i < riscv_reg_bits ; i ++ ) {
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if ((1 & (reg >> i )) == 0 )
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return i ;
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}
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- return 64 ;
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+ return riscv_reg_bits ;
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}
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static int set_trigger (struct target * target , unsigned int idx , riscv_reg_t tdata1 , riscv_reg_t tdata2 )
@@ -1576,6 +1576,7 @@ static int riscv_trigger_detect_hit_bits(struct target *target, int64_t *unique_
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// FIXME: Add hit bits support detection and caching
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RISCV_INFO (r );
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+ r -> need_single_step = true;
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riscv_reg_t tselect ;
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if (riscv_reg_get (target , & tselect , GDB_REGNO_TSELECT ) != ERROR_OK )
@@ -1601,18 +1602,29 @@ static int riscv_trigger_detect_hit_bits(struct target *target, int64_t *unique_
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break ;
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case CSR_TDATA1_TYPE_MCONTROL :
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hit_mask = CSR_MCONTROL_HIT ;
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+ if (get_field (tdata1 , CSR_MCONTROL_TIMING ) == CSR_MCONTROL_TIMING_AFTER )
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+ r -> need_single_step = false;
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break ;
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case CSR_TDATA1_TYPE_MCONTROL6 :
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hit_mask = CSR_MCONTROL6_HIT0 | CSR_MCONTROL6_HIT1 ;
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+ int hit0 = get_field (tdata1 , CSR_MCONTROL6_HIT0 );
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+ int hit1 = get_field (tdata1 , CSR_MCONTROL6_HIT1 );
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+ int trigger_retired_info = (hit1 << 1 ) | hit0 ;
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+ if (trigger_retired_info == CSR_MCONTROL6_HIT0_AFTER
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+ || trigger_retired_info == CSR_MCONTROL6_HIT0_IMMEDIATELY_AFTER )
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+ r -> need_single_step = false;
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break ;
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case CSR_TDATA1_TYPE_ICOUNT :
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hit_mask = CSR_ICOUNT_HIT ;
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+ r -> need_single_step = false;
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break ;
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case CSR_TDATA1_TYPE_ITRIGGER :
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hit_mask = CSR_ITRIGGER_HIT (riscv_xlen (target ));
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+ r -> need_single_step = false;
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break ;
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case CSR_TDATA1_TYPE_ETRIGGER :
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hit_mask = CSR_ETRIGGER_HIT (riscv_xlen (target ));
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+ r -> need_single_step = false;
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break ;
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default :
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LOG_TARGET_DEBUG (target , "Trigger %u has unknown type %d" , i , type );
@@ -2547,16 +2559,29 @@ static int resume_prep(struct target *target, int current,
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assert (target -> state == TARGET_HALTED );
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RISCV_INFO (r );
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+ riscv_reg_t dcsr ;
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+ if (riscv_reg_get (target , & dcsr , GDB_REGNO_DCSR ) != ERROR_OK )
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+ return ERROR_FAIL ;
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+
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if (!current && riscv_reg_set (target , GDB_REGNO_PC , address ) != ERROR_OK )
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return ERROR_FAIL ;
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if (handle_breakpoints ) {
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/* To be able to run off a trigger, we perform a step operation and then
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* resume. If handle_breakpoints is true then step temporarily disables
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- * pending breakpoints so we can safely perform the step. */
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- if (old_or_new_riscv_step_impl (target , current , address , handle_breakpoints ,
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- false /* callbacks are not called */ ) != ERROR_OK )
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- return ERROR_FAIL ;
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+ * pending breakpoints so we can safely perform the step.
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+ *
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+ * Two cases where single step is needed before resuming:
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+ * 1. ebreak used in software breakpoint;
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+ * 2. a trigger that is taken just before the instruction that triggered it is retired.
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+ */
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+ if (get_field (dcsr , CSR_DCSR_CAUSE ) == CSR_DCSR_CAUSE_EBREAK
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+ || (get_field (dcsr , CSR_DCSR_CAUSE ) == CSR_DCSR_CAUSE_TRIGGER
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+ && r -> need_single_step )) {
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+ if (old_or_new_riscv_step_impl (target , current , address , handle_breakpoints ,
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+ false /* callbacks are not called */ ) != ERROR_OK )
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+ return ERROR_FAIL ;
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+ }
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}
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if (r -> get_hart_state ) {
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