clk: Add rp1 clock driver

RP1 contains various PLLs and clocks for driving the hardware
blocks, so add a driver to configure these.

Signed-off-by: Phil Elwell <[email protected]>

drivers: clk: rp1: add GPCLK source muxes and additional PLL dividers

General-purpose clocks are routed (via a pad) to a large variety of
peripheral aux muxes, and themselves gather a large variety of source
clocks. Entries without a corresponding name string should not be
selected - they bring out internal test/debug clocks which may be
intermittent or very high frequency.

As the GPCLK inputs to peripheral muxes come from a pad, differentiate
the source name from the divider output name. This allows the
possibility of specifying an off-chip clock source to drive the internal
peripheral clock.

Signed-off-by: Jonathan Bell <[email protected]>

drivers: clk: rp1: constrain clock divider outputs to design maximums

Overclocking peripherals is generally a bad thing to do - so reject any
attempt to set a clock output higher than it should be.

Signed-off-by: Jonathan Bell <[email protected]>

clk: rp1: Reserve pll_audio* for clk_i2s

Prevent all clocks except clk_i2s from using the audio PLLs as sources,
so that clk_i2s may be allowed to change them as needed.

Signed-off-by: Phil Elwell <[email protected]>

clk: rp1: Allow clk_i2s to change the audio PLLs

Add dedicated code allowing the audio PLLs to be changed, enabling
perfect I2S clock generation. The slowest legal pll_audio_core and
pll_audio will be selected that leads to the required clk_i2s rate.

Signed-off-by: Phil Elwell <[email protected]>

clk: clk-rp1: Add "varsrc" clocks to represent MIPI byte clocks

Add a new class of clocks to RP1 to represent clock sources whose
frequency changes at run-time as a side-effect of some other driver.
Specifically this is for the two MIPI DSI byte-clock sources.

Signed-off-by: Nick Hollinghurst <[email protected]>

clk: clk-rp1: Don't crash on duplicate clocks

When using DTBs that don't match the kernel version, it's possible for
clock registration to fail. Handle that failure, in the hope that the
system can continue to boot, with a suitable error message.

Link: #6321

Signed-off-by: Phil Elwell <[email protected]>

Author: pelwell

drivers/clk/Kconfig

@@ -88,6 +88,13 @@ config COMMON_CLK_RK808
 	  These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
 	  Clkout1 is always on, Clkout2 can off by control register.
 
+config COMMON_CLK_RP1
+	tristate "Raspberry Pi RP1-based clock support"
+	depends on PCI || COMPILE_TEST
+	depends on COMMON_CLK
+	help
+	  Enable common clock framework support for Raspberry Pi RP1
+
 config COMMON_CLK_HI655X
 	tristate "Clock driver for Hi655x" if EXPERT
 	depends on (MFD_HI655X_PMIC || COMPILE_TEST)

drivers/clk/Makefile

@@ -70,6 +70,7 @@ obj-$(CONFIG_CLK_LS1028A_PLLDIG)	+= clk-plldig.o
 obj-$(CONFIG_COMMON_CLK_PWM)		+= clk-pwm.o
 obj-$(CONFIG_CLK_QORIQ)			+= clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_RK808)		+= clk-rk808.o
+obj-$(CONFIG_COMMON_CLK_RP1)		+= clk-rp1.o
 obj-$(CONFIG_COMMON_CLK_HI655X)		+= clk-hi655x.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)	+= clk-s2mps11.o
 obj-$(CONFIG_COMMON_CLK_SCMI)           += clk-scmi.o