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| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | +/* |
| 3 | + * This header provides constants for the PY MFD. |
| 4 | + */ |
| 5 | + |
| 6 | +#ifndef _RP1_H |
| 7 | +#define _RP1_H |
| 8 | + |
| 9 | +/* Address map */ |
| 10 | +#define RP1_SYSINFO_BASE 0x000000 |
| 11 | +#define RP1_TBMAN_BASE 0x004000 |
| 12 | +#define RP1_SYSCFG_BASE 0x008000 |
| 13 | +#define RP1_OTP_BASE 0x00c000 |
| 14 | +#define RP1_POWER_BASE 0x010000 |
| 15 | +#define RP1_RESETS_BASE 0x014000 |
| 16 | +#define RP1_CLOCKS_BANK_DEFAULT_BASE 0x018000 |
| 17 | +#define RP1_CLOCKS_BANK_VIDEO_BASE 0x01c000 |
| 18 | +#define RP1_PLL_SYS_BASE 0x020000 |
| 19 | +#define RP1_PLL_AUDIO_BASE 0x024000 |
| 20 | +#define RP1_PLL_VIDEO_BASE 0x028000 |
| 21 | +#define RP1_UART0_BASE 0x030000 |
| 22 | +#define RP1_UART1_BASE 0x034000 |
| 23 | +#define RP1_UART2_BASE 0x038000 |
| 24 | +#define RP1_UART3_BASE 0x03c000 |
| 25 | +#define RP1_UART4_BASE 0x040000 |
| 26 | +#define RP1_UART5_BASE 0x044000 |
| 27 | +#define RP1_SPI8_BASE 0x04c000 |
| 28 | +#define RP1_SPI0_BASE 0x050000 |
| 29 | +#define RP1_SPI1_BASE 0x054000 |
| 30 | +#define RP1_SPI2_BASE 0x058000 |
| 31 | +#define RP1_SPI3_BASE 0x05c000 |
| 32 | +#define RP1_SPI4_BASE 0x060000 |
| 33 | +#define RP1_SPI5_BASE 0x064000 |
| 34 | +#define RP1_SPI6_BASE 0x068000 |
| 35 | +#define RP1_SPI7_BASE 0x06c000 |
| 36 | +#define RP1_I2C0_BASE 0x070000 |
| 37 | +#define RP1_I2C1_BASE 0x074000 |
| 38 | +#define RP1_I2C2_BASE 0x078000 |
| 39 | +#define RP1_I2C3_BASE 0x07c000 |
| 40 | +#define RP1_I2C4_BASE 0x080000 |
| 41 | +#define RP1_I2C5_BASE 0x084000 |
| 42 | +#define RP1_I2C6_BASE 0x088000 |
| 43 | +#define RP1_AUDIO_IN_BASE 0x090000 |
| 44 | +#define RP1_AUDIO_OUT_BASE 0x094000 |
| 45 | +#define RP1_PWM0_BASE 0x098000 |
| 46 | +#define RP1_PWM1_BASE 0x09c000 |
| 47 | +#define RP1_I2S0_BASE 0x0a0000 |
| 48 | +#define RP1_I2S1_BASE 0x0a4000 |
| 49 | +#define RP1_I2S2_BASE 0x0a8000 |
| 50 | +#define RP1_TIMER_BASE 0x0ac000 |
| 51 | +#define RP1_SDIO0_APBS_BASE 0x0b0000 |
| 52 | +#define RP1_SDIO1_APBS_BASE 0x0b4000 |
| 53 | +#define RP1_BUSFABRIC_MONITOR_BASE 0x0c0000 |
| 54 | +#define RP1_BUSFABRIC_AXISHIM_BASE 0x0c4000 |
| 55 | +#define RP1_ADC_BASE 0x0c8000 |
| 56 | +#define RP1_IO_BANK0_BASE 0x0d0000 |
| 57 | +#define RP1_IO_BANK1_BASE 0x0d4000 |
| 58 | +#define RP1_IO_BANK2_BASE 0x0d8000 |
| 59 | +#define RP1_SYS_RIO0_BASE 0x0e0000 |
| 60 | +#define RP1_SYS_RIO1_BASE 0x0e4000 |
| 61 | +#define RP1_SYS_RIO2_BASE 0x0e8000 |
| 62 | +#define RP1_PADS_BANK0_BASE 0x0f0000 |
| 63 | +#define RP1_PADS_BANK1_BASE 0x0f4000 |
| 64 | +#define RP1_PADS_BANK2_BASE 0x0f8000 |
| 65 | +#define RP1_PADS_ETH_BASE 0x0fc000 |
| 66 | +#define RP1_ETH_IP_BASE 0x100000 |
| 67 | +#define RP1_ETH_CFG_BASE 0x104000 |
| 68 | +#define RP1_PCIE_APBS_BASE 0x108000 |
| 69 | +#define RP1_MIPI0_CSIDMA_BASE 0x110000 |
| 70 | +#define RP1_MIPI0_CSIHOST_BASE 0x114000 |
| 71 | +#define RP1_MIPI0_DSIDMA_BASE 0x118000 |
| 72 | +#define RP1_MIPI0_DSIHOST_BASE 0x11c000 |
| 73 | +#define RP1_MIPI0_MIPICFG_BASE 0x120000 |
| 74 | +#define RP1_MIPI0_ISP_BASE 0x124000 |
| 75 | +#define RP1_MIPI1_CSIDMA_BASE 0x128000 |
| 76 | +#define RP1_MIPI1_CSIHOST_BASE 0x12c000 |
| 77 | +#define RP1_MIPI1_DSIDMA_BASE 0x130000 |
| 78 | +#define RP1_MIPI1_DSIHOST_BASE 0x134000 |
| 79 | +#define RP1_MIPI1_MIPICFG_BASE 0x138000 |
| 80 | +#define RP1_MIPI1_ISP_BASE 0x13c000 |
| 81 | +#define RP1_VIDEO_OUT_CFG_BASE 0x140000 |
| 82 | +#define RP1_VIDEO_OUT_VEC_BASE 0x144000 |
| 83 | +#define RP1_VIDEO_OUT_DPI_BASE 0x148000 |
| 84 | +#define RP1_XOSC_BASE 0x150000 |
| 85 | +#define RP1_WATCHDOG_BASE 0x154000 |
| 86 | +#define RP1_DMA_TICK_BASE 0x158000 |
| 87 | +#define RP1_SDIO_CLOCKS_BASE 0x15c000 |
| 88 | +#define RP1_USBHOST0_APBS_BASE 0x160000 |
| 89 | +#define RP1_USBHOST1_APBS_BASE 0x164000 |
| 90 | +#define RP1_ROSC0_BASE 0x168000 |
| 91 | +#define RP1_ROSC1_BASE 0x16c000 |
| 92 | +#define RP1_VBUSCTRL_BASE 0x170000 |
| 93 | +#define RP1_TICKS_BASE 0x174000 |
| 94 | +#define RP1_PIO_APBS_BASE 0x178000 |
| 95 | +#define RP1_SDIO0_AHBLS_BASE 0x180000 |
| 96 | +#define RP1_SDIO1_AHBLS_BASE 0x184000 |
| 97 | +#define RP1_DMA_BASE 0x188000 |
| 98 | +#define RP1_RAM_BASE 0x1c0000 |
| 99 | +#define RP1_RAM_SIZE 0x020000 |
| 100 | +#define RP1_USBHOST0_AXIS_BASE 0x200000 |
| 101 | +#define RP1_USBHOST1_AXIS_BASE 0x300000 |
| 102 | +#define RP1_EXAC_BASE 0x400000 |
| 103 | + |
| 104 | +/* Interrupts */ |
| 105 | + |
| 106 | +#define RP1_INT_IO_BANK0 0 |
| 107 | +#define RP1_INT_IO_BANK1 1 |
| 108 | +#define RP1_INT_IO_BANK2 2 |
| 109 | +#define RP1_INT_AUDIO_IN 3 |
| 110 | +#define RP1_INT_AUDIO_OUT 4 |
| 111 | +#define RP1_INT_PWM0 5 |
| 112 | +#define RP1_INT_ETH 6 |
| 113 | +#define RP1_INT_I2C0 7 |
| 114 | +#define RP1_INT_I2C1 8 |
| 115 | +#define RP1_INT_I2C2 9 |
| 116 | +#define RP1_INT_I2C3 10 |
| 117 | +#define RP1_INT_I2C4 11 |
| 118 | +#define RP1_INT_I2C5 12 |
| 119 | +#define RP1_INT_I2C6 13 |
| 120 | +#define RP1_INT_I2S0 14 |
| 121 | +#define RP1_INT_I2S1 15 |
| 122 | +#define RP1_INT_I2S2 16 |
| 123 | +#define RP1_INT_SDIO0 17 |
| 124 | +#define RP1_INT_SDIO1 18 |
| 125 | +#define RP1_INT_SPI0 19 |
| 126 | +#define RP1_INT_SPI1 20 |
| 127 | +#define RP1_INT_SPI2 21 |
| 128 | +#define RP1_INT_SPI3 22 |
| 129 | +#define RP1_INT_SPI4 23 |
| 130 | +#define RP1_INT_SPI5 24 |
| 131 | +#define RP1_INT_UART0 25 |
| 132 | +#define RP1_INT_TIMER_0 26 |
| 133 | +#define RP1_INT_TIMER_1 27 |
| 134 | +#define RP1_INT_TIMER_2 28 |
| 135 | +#define RP1_INT_TIMER_3 29 |
| 136 | +#define RP1_INT_USBHOST0 30 |
| 137 | +#define RP1_INT_USBHOST0_0 31 |
| 138 | +#define RP1_INT_USBHOST0_1 32 |
| 139 | +#define RP1_INT_USBHOST0_2 33 |
| 140 | +#define RP1_INT_USBHOST0_3 34 |
| 141 | +#define RP1_INT_USBHOST1 35 |
| 142 | +#define RP1_INT_USBHOST1_0 36 |
| 143 | +#define RP1_INT_USBHOST1_1 37 |
| 144 | +#define RP1_INT_USBHOST1_2 38 |
| 145 | +#define RP1_INT_USBHOST1_3 39 |
| 146 | +#define RP1_INT_DMA 40 |
| 147 | +#define RP1_INT_PWM1 41 |
| 148 | +#define RP1_INT_UART1 42 |
| 149 | +#define RP1_INT_UART2 43 |
| 150 | +#define RP1_INT_UART3 44 |
| 151 | +#define RP1_INT_UART4 45 |
| 152 | +#define RP1_INT_UART5 46 |
| 153 | +#define RP1_INT_MIPI0 47 |
| 154 | +#define RP1_INT_MIPI1 48 |
| 155 | +#define RP1_INT_VIDEO_OUT 49 |
| 156 | +#define RP1_INT_PIO_0 50 |
| 157 | +#define RP1_INT_PIO_1 51 |
| 158 | +#define RP1_INT_ADC_FIFO 52 |
| 159 | +#define RP1_INT_PCIE_OUT 53 |
| 160 | +#define RP1_INT_SPI6 54 |
| 161 | +#define RP1_INT_SPI7 55 |
| 162 | +#define RP1_INT_SPI8 56 |
| 163 | +#define RP1_INT_SYSCFG 58 |
| 164 | +#define RP1_INT_CLOCKS_DEFAULT 59 |
| 165 | +#define RP1_INT_VBUSCTRL 60 |
| 166 | +#define RP1_INT_PROC_MISC 57 |
| 167 | +#define RP1_INT_END 61 |
| 168 | + |
| 169 | +/* DMA peripherals (for pacing) */ |
| 170 | +#define RP1_DMA_I2C0_RX 0x0 |
| 171 | +#define RP1_DMA_I2C0_TX 0x1 |
| 172 | +#define RP1_DMA_I2C1_RX 0x2 |
| 173 | +#define RP1_DMA_I2C1_TX 0x3 |
| 174 | +#define RP1_DMA_I2C2_RX 0x4 |
| 175 | +#define RP1_DMA_I2C2_TX 0x5 |
| 176 | +#define RP1_DMA_I2C3_RX 0x6 |
| 177 | +#define RP1_DMA_I2C3_TX 0x7 |
| 178 | +#define RP1_DMA_I2C4_RX 0x8 |
| 179 | +#define RP1_DMA_I2C4_TX 0x9 |
| 180 | +#define RP1_DMA_I2C5_RX 0xa |
| 181 | +#define RP1_DMA_I2C5_TX 0xb |
| 182 | +#define RP1_DMA_SPI0_RX 0xc |
| 183 | +#define RP1_DMA_SPI0_TX 0xd |
| 184 | +#define RP1_DMA_SPI1_RX 0xe |
| 185 | +#define RP1_DMA_SPI1_TX 0xf |
| 186 | +#define RP1_DMA_SPI2_RX 0x10 |
| 187 | +#define RP1_DMA_SPI2_TX 0x11 |
| 188 | +#define RP1_DMA_SPI3_RX 0x12 |
| 189 | +#define RP1_DMA_SPI3_TX 0x13 |
| 190 | +#define RP1_DMA_SPI4_RX 0x14 |
| 191 | +#define RP1_DMA_SPI4_TX 0x15 |
| 192 | +#define RP1_DMA_SPI5_RX 0x16 |
| 193 | +#define RP1_DMA_SPI5_TX 0x17 |
| 194 | +#define RP1_DMA_PWM0 0x18 |
| 195 | +#define RP1_DMA_UART0_RX 0x19 |
| 196 | +#define RP1_DMA_UART0_TX 0x1a |
| 197 | +#define RP1_DMA_AUDIO_IN_CH0 0x1b |
| 198 | +#define RP1_DMA_AUDIO_IN_CH1 0x1c |
| 199 | +#define RP1_DMA_AUDIO_OUT 0x1d |
| 200 | +#define RP1_DMA_PWM1 0x1e |
| 201 | +#define RP1_DMA_I2S0_RX 0x1f |
| 202 | +#define RP1_DMA_I2S0_TX 0x20 |
| 203 | +#define RP1_DMA_I2S1_RX 0x21 |
| 204 | +#define RP1_DMA_I2S1_TX 0x22 |
| 205 | +#define RP1_DMA_I2S2_RX 0x23 |
| 206 | +#define RP1_DMA_I2S2_TX 0x24 |
| 207 | +#define RP1_DMA_UART1_RX 0x25 |
| 208 | +#define RP1_DMA_UART1_TX 0x26 |
| 209 | +#define RP1_DMA_UART2_RX 0x27 |
| 210 | +#define RP1_DMA_UART2_TX 0x28 |
| 211 | +#define RP1_DMA_UART3_RX 0x29 |
| 212 | +#define RP1_DMA_UART3_TX 0x2a |
| 213 | +#define RP1_DMA_UART4_RX 0x2b |
| 214 | +#define RP1_DMA_UART4_TX 0x2c |
| 215 | +#define RP1_DMA_UART5_RX 0x2d |
| 216 | +#define RP1_DMA_UART5_TX 0x2e |
| 217 | +#define RP1_DMA_ADC 0x2f |
| 218 | +#define RP1_DMA_DMA_TICK_TICK0 0x30 |
| 219 | +#define RP1_DMA_DMA_TICK_TICK1 0x31 |
| 220 | +#define RP1_DMA_SPI6_RX 0x32 |
| 221 | +#define RP1_DMA_SPI6_TX 0x33 |
| 222 | +#define RP1_DMA_SPI7_RX 0x34 |
| 223 | +#define RP1_DMA_SPI7_TX 0x35 |
| 224 | +#define RP1_DMA_SPI8_RX 0x36 |
| 225 | +#define RP1_DMA_SPI8_TX 0x37 |
| 226 | +#define RP1_DMA_PIO_CH0_TX 0x38 |
| 227 | +#define RP1_DMA_PIO_CH0_RX 0x39 |
| 228 | +#define RP1_DMA_PIO_CH1_TX 0x3a |
| 229 | +#define RP1_DMA_PIO_CH1_RX 0x3b |
| 230 | +#define RP1_DMA_PIO_CH2_TX 0x3c |
| 231 | +#define RP1_DMA_PIO_CH2_RX 0x3d |
| 232 | +#define RP1_DMA_PIO_CH3_TX 0x3e |
| 233 | +#define RP1_DMA_PIO_CH3_RX 0x3f |
| 234 | + |
| 235 | +#endif |
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