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Merge branch 'raspberrypi:rpi-6.12.y' into rpi-6.12.y
2 parents 02b40b6 + 28d1e43 commit 5321fb8

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10 files changed

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-106
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10 files changed

+303
-106
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‎Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml

+66-11
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
77
title: Broadcom V3D GPU
88

99
maintainers:
10-
- Eric Anholt <[email protected]>
10+
- Maíra Canal <[email protected]>
1111
- Nicolas Saenz Julienne <[email protected]>
1212

1313
properties:
@@ -23,20 +23,12 @@ properties:
2323
- brcm,7278-v3d
2424

2525
reg:
26-
items:
27-
- description: hub register (required)
28-
- description: core0 register (required)
29-
- description: GCA cache controller register (if GCA controller present)
30-
- description: bridge register (if no external reset controller)
3126
minItems: 2
27+
maxItems: 4
3228

3329
reg-names:
34-
items:
35-
- const: hub
36-
- const: core0
37-
- enum: [ bridge, gca ]
38-
- enum: [ bridge, gca ]
3930
minItems: 2
31+
maxItems: 4
4032

4133
interrupts:
4234
items:
@@ -59,6 +51,69 @@ required:
5951
- reg-names
6052
- interrupts
6153

54+
allOf:
55+
- if:
56+
properties:
57+
compatible:
58+
contains:
59+
enum:
60+
- brcm,2711-v3d
61+
- brcm,7278-v3d
62+
then:
63+
properties:
64+
reg:
65+
items:
66+
- description: hub register (required)
67+
- description: core0 register (required)
68+
- description: bridge register (if no external reset controller)
69+
reg-names:
70+
items:
71+
- const: hub
72+
- const: core0
73+
- const: bridge
74+
- if:
75+
properties:
76+
compatible:
77+
contains:
78+
const: brcm,2712-v3d
79+
then:
80+
properties:
81+
reg:
82+
items:
83+
- description: hub register (required)
84+
- description: core0 register (required)
85+
- description: SMS register (required)
86+
- description: bridge register (if no external reset controller)
87+
minItems: 3
88+
reg-names:
89+
items:
90+
- const: hub
91+
- const: core0
92+
- const: sms
93+
- const: bridge
94+
minItems: 3
95+
- if:
96+
properties:
97+
compatible:
98+
contains:
99+
const: brcm,7268-v3d
100+
then:
101+
properties:
102+
reg:
103+
items:
104+
- description: hub register (required)
105+
- description: core0 register (required)
106+
- description: GCA cache controller register (required)
107+
- description: bridge register (if no external reset controller)
108+
minItems: 3
109+
reg-names:
110+
items:
111+
- const: hub
112+
- const: core0
113+
- enum: [ bridge, gca ]
114+
- enum: [ bridge, gca ]
115+
minItems: 3
116+
62117
additionalProperties: false
63118

64119
examples:

‎arch/arm64/boot/dts/broadcom/bcm2712-ds.dtsi

+3-2
Original file line numberDiff line numberDiff line change
@@ -599,8 +599,9 @@
599599
v3d: v3d@2000000 {
600600
compatible = "brcm,2712-v3d";
601601
reg = <0x10 0x02000000 0x0 0x4000>,
602-
<0x10 0x02008000 0x0 0x6000>;
603-
reg-names = "hub", "core0";
602+
<0x10 0x02008000 0x0 0x6000>,
603+
<0x10 0x02030800 0x0 0x0700>;
604+
reg-names = "hub", "core0", "sms";
604605

605606
power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
606607
resets = <&pm BCM2835_RESET_V3D>;

‎drivers/gpu/drm/v3d/v3d_debugfs.c

+63-63
Original file line numberDiff line numberDiff line change
@@ -21,74 +21,74 @@ struct v3d_reg_def {
2121
};
2222

2323
static const struct v3d_reg_def v3d_hub_reg_defs[] = {
24-
REGDEF(33, 42, V3D_HUB_AXICFG),
25-
REGDEF(33, 71, V3D_HUB_UIFCFG),
26-
REGDEF(33, 71, V3D_HUB_IDENT0),
27-
REGDEF(33, 71, V3D_HUB_IDENT1),
28-
REGDEF(33, 71, V3D_HUB_IDENT2),
29-
REGDEF(33, 71, V3D_HUB_IDENT3),
30-
REGDEF(33, 71, V3D_HUB_INT_STS),
31-
REGDEF(33, 71, V3D_HUB_INT_MSK_STS),
32-
33-
REGDEF(33, 71, V3D_MMU_CTL),
34-
REGDEF(33, 71, V3D_MMU_VIO_ADDR),
35-
REGDEF(33, 71, V3D_MMU_VIO_ID),
36-
REGDEF(33, 71, V3D_MMU_DEBUG_INFO),
37-
38-
REGDEF(71, 71, V3D_GMP_STATUS(71)),
39-
REGDEF(71, 71, V3D_GMP_CFG(71)),
40-
REGDEF(71, 71, V3D_GMP_VIO_ADDR(71)),
24+
REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_HUB_AXICFG),
25+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_UIFCFG),
26+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT0),
27+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT1),
28+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT2),
29+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT3),
30+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_STS),
31+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_MSK_STS),
32+
33+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_CTL),
34+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ADDR),
35+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ID),
36+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_DEBUG_INFO),
37+
38+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_STATUS(71)),
39+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_CFG(71)),
40+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_VIO_ADDR(71)),
4141
};
4242

4343
static const struct v3d_reg_def v3d_gca_reg_defs[] = {
44-
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN),
45-
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK),
44+
REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN),
45+
REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN_ACK),
4646
};
4747

4848
static const struct v3d_reg_def v3d_core_reg_defs[] = {
49-
REGDEF(33, 71, V3D_CTL_IDENT0),
50-
REGDEF(33, 71, V3D_CTL_IDENT1),
51-
REGDEF(33, 71, V3D_CTL_IDENT2),
52-
REGDEF(33, 71, V3D_CTL_MISCCFG),
53-
REGDEF(33, 71, V3D_CTL_INT_STS),
54-
REGDEF(33, 71, V3D_CTL_INT_MSK_STS),
55-
REGDEF(33, 71, V3D_CLE_CT0CS),
56-
REGDEF(33, 71, V3D_CLE_CT0CA),
57-
REGDEF(33, 71, V3D_CLE_CT0EA),
58-
REGDEF(33, 71, V3D_CLE_CT1CS),
59-
REGDEF(33, 71, V3D_CLE_CT1CA),
60-
REGDEF(33, 71, V3D_CLE_CT1EA),
61-
62-
REGDEF(33, 71, V3D_PTB_BPCA),
63-
REGDEF(33, 71, V3D_PTB_BPCS),
64-
65-
REGDEF(33, 42, V3D_GMP_STATUS(33)),
66-
REGDEF(33, 42, V3D_GMP_CFG(33)),
67-
REGDEF(33, 42, V3D_GMP_VIO_ADDR(33)),
68-
69-
REGDEF(33, 71, V3D_ERR_FDBGO),
70-
REGDEF(33, 71, V3D_ERR_FDBGB),
71-
REGDEF(33, 71, V3D_ERR_FDBGS),
72-
REGDEF(33, 71, V3D_ERR_STAT),
49+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT0),
50+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT1),
51+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT2),
52+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_MISCCFG),
53+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_STS),
54+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_MSK_STS),
55+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CS),
56+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CA),
57+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0EA),
58+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CS),
59+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CA),
60+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1EA),
61+
62+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCA),
63+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCS),
64+
65+
REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_STATUS(33)),
66+
REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_CFG(33)),
67+
REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_VIO_ADDR(33)),
68+
69+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGO),
70+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGB),
71+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGS),
72+
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_STAT),
7373
};
7474

7575
static const struct v3d_reg_def v3d_csd_reg_defs[] = {
76-
REGDEF(41, 71, V3D_CSD_STATUS),
77-
REGDEF(41, 42, V3D_CSD_CURRENT_CFG0(41)),
78-
REGDEF(41, 42, V3D_CSD_CURRENT_CFG1(41)),
79-
REGDEF(41, 42, V3D_CSD_CURRENT_CFG2(41)),
80-
REGDEF(41, 42, V3D_CSD_CURRENT_CFG3(41)),
81-
REGDEF(41, 42, V3D_CSD_CURRENT_CFG4(41)),
82-
REGDEF(41, 42, V3D_CSD_CURRENT_CFG5(41)),
83-
REGDEF(41, 42, V3D_CSD_CURRENT_CFG6(41)),
84-
REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
85-
REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
86-
REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),
87-
REGDEF(71, 71, V3D_CSD_CURRENT_CFG3(71)),
88-
REGDEF(71, 71, V3D_CSD_CURRENT_CFG4(71)),
89-
REGDEF(71, 71, V3D_CSD_CURRENT_CFG5(71)),
90-
REGDEF(71, 71, V3D_CSD_CURRENT_CFG6(71)),
91-
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7),
76+
REGDEF(V3D_GEN_41, V3D_GEN_71, V3D_CSD_STATUS),
77+
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG0(41)),
78+
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG1(41)),
79+
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG2(41)),
80+
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG3(41)),
81+
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG4(41)),
82+
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG5(41)),
83+
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG6(41)),
84+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG0(71)),
85+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG1(71)),
86+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG2(71)),
87+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG3(71)),
88+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG4(71)),
89+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG5(71)),
90+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG6(71)),
91+
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG7),
9292
};
9393

9494
static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
@@ -164,7 +164,7 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
164164
str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
165165
seq_printf(m, "TFU: %s\n",
166166
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
167-
if (v3d->ver <= 42) {
167+
if (v3d->ver <= V3D_GEN_42) {
168168
seq_printf(m, "TSY: %s\n",
169169
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
170170
}
@@ -196,11 +196,11 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
196196
seq_printf(m, " QPUs: %d\n", nslc * qups);
197197
seq_printf(m, " Semaphores: %d\n",
198198
V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
199-
if (v3d->ver <= 42) {
199+
if (v3d->ver <= V3D_GEN_42) {
200200
seq_printf(m, " BCG int: %d\n",
201201
(ident2 & V3D_IDENT2_BCG_INT) != 0);
202202
}
203-
if (v3d->ver < 40) {
203+
if (v3d->ver < V3D_GEN_41) {
204204
seq_printf(m, " Override TMU: %d\n",
205205
(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
206206
}
@@ -234,7 +234,7 @@ static int v3d_measure_clock(struct seq_file *m, void *unused)
234234
int core = 0;
235235
int measure_ms = 1000;
236236

237-
if (v3d->ver >= 40) {
237+
if (v3d->ver >= V3D_GEN_41) {
238238
int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver);
239239
V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
240240
V3D_SET_FIELD_VER(cycle_count_reg,

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