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crypto: qat - expose deflate through acomp api for QAT GEN2
jira LE-1907 Rebuild_History Non-Buildable kernel-rt-5.14.0-284.30.1.rt14.315.el9_2 commit-author Giovanni Cabiddu <[email protected]> commit 1198ae5 Add infrastructure for implementing the acomp APIs in the QAT driver and expose the deflate algorithm for QAT GEN2 devices. This adds (1) the compression service which includes logic to create, allocate and handle compression instances; (2) logic to create configuration entries at probe time for the compression instances; (3) updates to the firmware API for allowing the compression service; and; (4) a back-end for deflate that implements the acomp api for QAT GEN2 devices. The implementation configures the device to produce data compressed statically, optimized for throughput over compression ratio. Signed-off-by: Giovanni Cabiddu <[email protected]> Reviewed-by: Wojciech Ziemba <[email protected]> Reviewed-by: Adam Guerin <[email protected]> Signed-off-by: Herbert Xu <[email protected]> (cherry picked from commit 1198ae5) Signed-off-by: Jonathan Maple <[email protected]>
1 parent 2266421 commit c868e84

24 files changed

+1447
-12
lines changed

‎drivers/crypto/qat/qat_4xxx/adf_drv.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,12 @@ int adf_crypto_dev_config(struct adf_accel_dev *accel_dev)
155155
if (ret)
156156
goto err;
157157

158+
val = 0;
159+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,
160+
&val, ADF_DEC);
161+
if (ret)
162+
goto err;
163+
158164
set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
159165
return 0;
160166
err:

‎drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
#include <adf_accel_devices.h>
44
#include <adf_common_drv.h>
55
#include <adf_gen2_config.h>
6+
#include <adf_gen2_dc.h>
67
#include <adf_gen2_hw_data.h>
78
#include <adf_gen2_pfvf.h>
89
#include "adf_c3xxx_hw_data.h"
@@ -129,6 +130,7 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
129130

130131
adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
131132
adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
133+
adf_gen2_init_dc_ops(&hw_data->dc_ops);
132134
}
133135

134136
void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data)

‎drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
#include <adf_accel_devices.h>
44
#include <adf_common_drv.h>
55
#include <adf_gen2_config.h>
6+
#include <adf_gen2_dc.h>
67
#include <adf_gen2_hw_data.h>
78
#include <adf_gen2_pfvf.h>
89
#include <adf_pfvf_vf_msg.h>
@@ -91,6 +92,7 @@ void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
9192
adf_devmgr_update_class_index(hw_data);
9293
adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
9394
adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
95+
adf_gen2_init_dc_ops(&hw_data->dc_ops);
9496
}
9597

9698
void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)

‎drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
#include <adf_accel_devices.h>
44
#include <adf_common_drv.h>
55
#include <adf_gen2_config.h>
6+
#include <adf_gen2_dc.h>
67
#include <adf_gen2_hw_data.h>
78
#include <adf_gen2_pfvf.h>
89
#include "adf_c62x_hw_data.h"
@@ -131,6 +132,7 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
131132

132133
adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
133134
adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
135+
adf_gen2_init_dc_ops(&hw_data->dc_ops);
134136
}
135137

136138
void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data)

‎drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
#include <adf_accel_devices.h>
44
#include <adf_common_drv.h>
55
#include <adf_gen2_config.h>
6+
#include <adf_gen2_dc.h>
67
#include <adf_gen2_hw_data.h>
78
#include <adf_gen2_pfvf.h>
89
#include <adf_pfvf_vf_msg.h>
@@ -91,6 +92,7 @@ void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
9192
adf_devmgr_update_class_index(hw_data);
9293
adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
9394
adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
95+
adf_gen2_init_dc_ops(&hw_data->dc_ops);
9496
}
9597

9698
void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data)

‎drivers/crypto/qat/qat_common/Makefile

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,10 @@ intel_qat-objs := adf_cfg.o \
1515
adf_gen2_config.o \
1616
adf_gen4_hw_data.o \
1717
adf_gen4_pm.o \
18+
adf_gen2_dc.o \
1819
qat_crypto.o \
20+
qat_compression.o \
21+
qat_comp_algs.o \
1922
qat_algs.o \
2023
qat_asym_algs.o \
2124
qat_algs_send.o \

‎drivers/crypto/qat/qat_common/adf_accel_devices.h

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -163,6 +163,10 @@ struct adf_pfvf_ops {
163163
u32 pfvf_offset, u8 compat_ver);
164164
};
165165

166+
struct adf_dc_ops {
167+
void (*build_deflate_ctx)(void *ctx);
168+
};
169+
166170
struct adf_hw_device_data {
167171
struct adf_hw_device_class *dev_class;
168172
u32 (*get_accel_mask)(struct adf_hw_device_data *self);
@@ -202,6 +206,7 @@ struct adf_hw_device_data {
202206
int (*dev_config)(struct adf_accel_dev *accel_dev);
203207
struct adf_pfvf_ops pfvf_ops;
204208
struct adf_hw_csr_ops csr_ops;
209+
struct adf_dc_ops dc_ops;
205210
const char *fw_name;
206211
const char *fw_mmp_name;
207212
u32 fuses;
@@ -247,6 +252,7 @@ struct adf_hw_device_data {
247252
#define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
248253
#define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
249254
#define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops)
255+
#define GET_DC_OPS(accel_dev) (&(accel_dev)->hw_device->dc_ops)
250256
#define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
251257

252258
struct adf_admin_comms;
@@ -266,13 +272,21 @@ struct adf_accel_vf_info {
266272
u8 vf_compat_ver;
267273
};
268274

275+
struct adf_dc_data {
276+
u8 *ovf_buff;
277+
size_t ovf_buff_sz;
278+
dma_addr_t ovf_buff_p;
279+
};
280+
269281
struct adf_accel_dev {
270282
struct adf_etr_data *transport;
271283
struct adf_hw_device_data *hw_device;
272284
struct adf_cfg_device_data *cfg;
273285
struct adf_fw_loader_data *fw_loader;
274286
struct adf_admin_comms *admin;
287+
struct adf_dc_data *dc_data;
275288
struct list_head crypto_list;
289+
struct list_head compression_list;
276290
unsigned long status;
277291
atomic_t ref_count;
278292
struct dentry *debugfs_dir;

‎drivers/crypto/qat/qat_common/adf_cfg_strings.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#define ADF_ETRMGR_BANK "Bank"
2121
#define ADF_RING_SYM_BANK_NUM "BankSymNumber"
2222
#define ADF_RING_ASYM_BANK_NUM "BankAsymNumber"
23+
#define ADF_RING_DC_BANK_NUM "BankDcNumber"
2324
#define ADF_CY "Cy"
2425
#define ADF_DC "Dc"
2526
#define ADF_CFG_DC "dc"

‎drivers/crypto/qat/qat_common/adf_common_drv.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,14 @@ void qat_algs_unregister(void);
120120
int qat_asym_algs_register(void);
121121
void qat_asym_algs_unregister(void);
122122

123+
struct qat_compression_instance *qat_compression_get_instance_node(int node);
124+
void qat_compression_put_instance(struct qat_compression_instance *inst);
125+
int qat_compression_register(void);
126+
int qat_compression_unregister(void);
127+
int qat_comp_algs_register(void);
128+
void qat_comp_algs_unregister(void);
129+
void qat_comp_alg_callback(void *resp);
130+
123131
int adf_isr_resource_alloc(struct adf_accel_dev *accel_dev);
124132
void adf_isr_resource_free(struct adf_accel_dev *accel_dev);
125133
int adf_vf_isr_resource_alloc(struct adf_accel_dev *accel_dev);

‎drivers/crypto/qat/qat_common/adf_ctl_drv.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -438,8 +438,13 @@ static int __init adf_register_ctl_device_driver(void)
438438
if (qat_crypto_register())
439439
goto err_crypto_register;
440440

441+
if (qat_compression_register())
442+
goto err_compression_register;
443+
441444
return 0;
442445

446+
err_compression_register:
447+
qat_crypto_unregister();
443448
err_crypto_register:
444449
adf_exit_vf_wq();
445450
err_vf_wq:
@@ -463,6 +468,7 @@ static void __exit adf_unregister_ctl_device_driver(void)
463468
adf_exit_vf_wq();
464469
adf_exit_pf_wq();
465470
qat_crypto_unregister();
471+
qat_compression_unregister();
466472
adf_clean_vf_map(false);
467473
mutex_destroy(&adf_ctl_lock);
468474
}

‎drivers/crypto/qat/qat_common/adf_gen2_config.c

Lines changed: 87 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#include "adf_gen2_config.h"
77
#include "adf_common_drv.h"
88
#include "qat_crypto.h"
9+
#include "qat_compression.h"
910
#include "adf_transport_access_macros.h"
1011

1112
static int adf_gen2_crypto_dev_config(struct adf_accel_dev *accel_dev)
@@ -23,14 +24,6 @@ static int adf_gen2_crypto_dev_config(struct adf_accel_dev *accel_dev)
2324
else
2425
instances = 0;
2526

26-
ret = adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC);
27-
if (ret)
28-
goto err;
29-
30-
ret = adf_cfg_section_add(accel_dev, "Accelerator0");
31-
if (ret)
32-
goto err;
33-
3427
for (i = 0; i < instances; i++) {
3528
val = i;
3629
snprintf(key, sizeof(key), ADF_CY "%d" ADF_RING_ASYM_BANK_NUM, i);
@@ -108,10 +101,68 @@ static int adf_gen2_crypto_dev_config(struct adf_accel_dev *accel_dev)
108101
if (ret)
109102
goto err;
110103

111-
set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
112-
return 0;
104+
return ret;
105+
106+
err:
107+
dev_err(&GET_DEV(accel_dev), "Failed to add configuration for crypto\n");
108+
return ret;
109+
}
110+
111+
static int adf_gen2_comp_dev_config(struct adf_accel_dev *accel_dev)
112+
{
113+
char key[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
114+
int banks = GET_MAX_BANKS(accel_dev);
115+
int cpus = num_online_cpus();
116+
unsigned long val;
117+
int instances;
118+
int ret;
119+
int i;
120+
121+
if (adf_hw_dev_has_compression(accel_dev))
122+
instances = min(cpus, banks);
123+
else
124+
instances = 0;
125+
126+
for (i = 0; i < instances; i++) {
127+
val = i;
128+
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_BANK_NUM, i);
129+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
130+
key, &val, ADF_DEC);
131+
if (ret)
132+
goto err;
133+
134+
val = 512;
135+
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_SIZE, i);
136+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
137+
key, &val, ADF_DEC);
138+
if (ret)
139+
goto err;
140+
141+
val = 6;
142+
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_TX, i);
143+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
144+
key, &val, ADF_DEC);
145+
if (ret)
146+
goto err;
147+
148+
val = 14;
149+
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_RX, i);
150+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
151+
key, &val, ADF_DEC);
152+
if (ret)
153+
goto err;
154+
}
155+
156+
val = i;
157+
ret = adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC, ADF_NUM_DC,
158+
&val, ADF_DEC);
159+
if (ret)
160+
return ret;
161+
162+
return ret;
163+
113164
err:
114-
dev_err(&GET_DEV(accel_dev), "Failed to start QAT accel dev\n");
165+
dev_err(&GET_DEV(accel_dev), "Failed to add configuration for compression\n");
115166
return ret;
116167
}
117168

@@ -126,6 +177,30 @@ static int adf_gen2_crypto_dev_config(struct adf_accel_dev *accel_dev)
126177
*/
127178
int adf_gen2_dev_config(struct adf_accel_dev *accel_dev)
128179
{
129-
return adf_gen2_crypto_dev_config(accel_dev);
180+
int ret;
181+
182+
ret = adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC);
183+
if (ret)
184+
goto err;
185+
186+
ret = adf_cfg_section_add(accel_dev, "Accelerator0");
187+
if (ret)
188+
goto err;
189+
190+
ret = adf_gen2_crypto_dev_config(accel_dev);
191+
if (ret)
192+
goto err;
193+
194+
ret = adf_gen2_comp_dev_config(accel_dev);
195+
if (ret)
196+
goto err;
197+
198+
set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
199+
200+
return ret;
201+
202+
err:
203+
dev_err(&GET_DEV(accel_dev), "Failed to configure QAT driver\n");
204+
return ret;
130205
}
131206
EXPORT_SYMBOL_GPL(adf_gen2_dev_config);

‎drivers/crypto/qat/qat_common/adf_gen2_dc.c

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,70 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/* Copyright(c) 2022 Intel Corporation */
3+
#include "adf_accel_devices.h"
4+
#include "adf_gen2_dc.h"
5+
#include "icp_qat_fw_comp.h"
6+
7+
static void qat_comp_build_deflate_ctx(void *ctx)
8+
{
9+
struct icp_qat_fw_comp_req *req_tmpl = (struct icp_qat_fw_comp_req *)ctx;
10+
struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
11+
struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
12+
struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
13+
struct icp_qat_fw_comp_cd_hdr *comp_cd_ctrl = &req_tmpl->comp_cd_ctrl;
14+
15+
memset(req_tmpl, 0, sizeof(*req_tmpl));
16+
header->hdr_flags =
17+
ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
18+
header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
19+
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
20+
header->comn_req_flags =
21+
ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
22+
QAT_COMN_PTR_TYPE_SGL);
23+
header->serv_specif_flags =
24+
ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
25+
ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
26+
ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
27+
ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
28+
ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
29+
cd_pars->u.sl.comp_slice_cfg_word[0] =
30+
ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_COMPRESS,
31+
ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
32+
ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
33+
ICP_QAT_HW_COMPRESSION_DEPTH_1,
34+
ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
35+
req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
36+
req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
37+
req_pars->req_par_flags =
38+
ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
39+
ICP_QAT_FW_COMP_EOP,
40+
ICP_QAT_FW_COMP_BFINAL,
41+
ICP_QAT_FW_COMP_CNV,
42+
ICP_QAT_FW_COMP_CNV_RECOVERY,
43+
ICP_QAT_FW_COMP_NO_CNV_DFX,
44+
ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
45+
ICP_QAT_FW_COMP_NO_XXHASH_ACC,
46+
ICP_QAT_FW_COMP_CNV_ERROR_NONE,
47+
ICP_QAT_FW_COMP_NO_APPEND_CRC,
48+
ICP_QAT_FW_COMP_NO_DROP_DATA);
49+
ICP_QAT_FW_COMN_NEXT_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
50+
ICP_QAT_FW_COMN_CURR_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_COMP);
51+
52+
/* Fill second half of the template for decompression */
53+
memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
54+
req_tmpl++;
55+
header = &req_tmpl->comn_hdr;
56+
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
57+
cd_pars = &req_tmpl->cd_pars;
58+
cd_pars->u.sl.comp_slice_cfg_word[0] =
59+
ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS,
60+
ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
61+
ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
62+
ICP_QAT_HW_COMPRESSION_DEPTH_1,
63+
ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
64+
}
65+
66+
void adf_gen2_init_dc_ops(struct adf_dc_ops *dc_ops)
67+
{
68+
dc_ops->build_deflate_ctx = qat_comp_build_deflate_ctx;
69+
}
70+
EXPORT_SYMBOL_GPL(adf_gen2_init_dc_ops);

‎drivers/crypto/qat/qat_common/adf_gen2_dc.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
/* Copyright(c) 2022 Intel Corporation */
3+
#ifndef ADF_GEN2_DC_H
4+
#define ADF_GEN2_DC_H
5+
6+
#include "adf_accel_devices.h"
7+
8+
void adf_gen2_init_dc_ops(struct adf_dc_ops *dc_ops);
9+
10+
#endif /* ADF_GEN2_DC_H */

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