Skip to content

Commit 56533cb

Browse files
Merge pull request #300 from pulp-platform/feature/id_slize_map
axi_id_serialize: Add optional ID base and map parameters
2 parents 45cfe01 + ff78b04 commit 56533cb

File tree

1 file changed

+31
-3
lines changed

1 file changed

+31
-3
lines changed

src/axi_id_serialize.sv

+31-3
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,17 @@ module axi_id_serialize #(
5555
/// Request struct type of the AXI4+ATOP master port
5656
parameter type mst_req_t = logic,
5757
/// Response struct type of the AXI4+ATOP master port
58-
parameter type mst_resp_t = logic
58+
parameter type mst_resp_t = logic,
59+
/// A custom offset (modulo `AxiMstPortMaxUniqIds`, ignored for input IDs remapped through
60+
/// `IdMap`) for the assigned output IDs.
61+
parameter int unsigned MstIdBaseOffset = 32'd0,
62+
/// Explicit input-output ID map. If an input ID `id` does not appear in this mapping (default),
63+
/// it is simply mapped to the output ID `id % AxiMstPortMaxUniqIds`. If `id` appears in more
64+
/// than one entry, it is matched to the *last* matching entry's output ID.
65+
/// Number of Entries in the explicit ID map (default: None)
66+
parameter int unsigned IdMapNumEntries = 32'd0,
67+
/// Explicit ID map; index [0] in each entry is the input ID to match, index [1] the output ID.
68+
parameter int unsigned IdMap [IdMapNumEntries-1:0][0:1] = '{default: '{32'b0, 32'b0}}
5969
) (
6070
/// Rising-edge clock of both ports
6171
input logic clk_i,
@@ -143,9 +153,27 @@ module axi_id_serialize #(
143153
/// R channel at master port
144154
`AXI_TYPEDEF_R_CHAN_T(mst_r_t, data_t, mst_id_t, user_t)
145155

156+
/// Type for slave ID map
157+
typedef mst_id_t [2**AxiSlvPortIdWidth-1:0] slv_id_map_t;
158+
159+
/// Resolve target output ID for each possible input ID as a parameter
160+
function automatic slv_id_map_t map_slv_ids();
161+
slv_id_map_t ret = '0;
162+
// Populate output with default mapping, including `MstIdBaseOffset`
163+
for (int unsigned i = 0; i < 2**AxiSlvPortIdWidth; ++i)
164+
ret[i] = (i + MstIdBaseOffset) % AxiMstPortMaxUniqIds;
165+
// For each explicitly mapped input ID, set the desired output ID
166+
for (int unsigned i = 0; i < IdMapNumEntries; ++i)
167+
ret[IdMap[i][0]] = IdMap[i][1];
168+
return ret;
169+
endfunction
170+
171+
/// Input-to-output ID map used
172+
localparam slv_id_map_t SlvIdMap = map_slv_ids();
173+
146174
select_t slv_aw_select, slv_ar_select;
147-
assign slv_aw_select = select_t'(slv_req_i.aw.id % AxiMstPortMaxUniqIds); // TODO: customizable base
148-
assign slv_ar_select = select_t'(slv_req_i.ar.id % AxiMstPortMaxUniqIds);
175+
assign slv_aw_select = select_t'(SlvIdMap[slv_req_i.aw.id]);
176+
assign slv_ar_select = select_t'(SlvIdMap[slv_req_i.ar.id]);
149177

150178
slv_req_t [AxiMstPortMaxUniqIds-1:0] to_serializer_reqs;
151179
slv_resp_t [AxiMstPortMaxUniqIds-1:0] to_serializer_resps;

0 commit comments

Comments
 (0)