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perlindgrenperlindgren
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vips wip
1 parent 450c074 commit 49517ae

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9 files changed

+349
-138
lines changed

9 files changed

+349
-138
lines changed

‎src/adder.veryl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
// src/adder.veryl
2+
13
module Adder #(
24
param Width: u32 = 32,
35
) (

‎src/alu.veryl‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
// src/alu.veryl
2+
13
module Alu #(
24
param Width: u32 = 32,
35
) (
@@ -10,7 +12,6 @@ module Alu #(
1012
c : output logic ,
1113
z : output logic ,
1214
) {
13-
/* verilator lint_off UNOPTFLAT */
1415
var sum : logic<Width>;
1516
var extend_in : logic ;
1617
var extend_out: logic<Width>;
@@ -44,15 +45,14 @@ module Alu #(
4445
// sub alu opration code
4546
// 0 00 and
4647
// 0 01 or
47-
// 0 10 add
48+
// 0 10 add
4849
// 1 10 sub
4950
// 1 11 slt
5051
inst mux: Mux4 #(
5152
Width ,
5253
) (
53-
i: {a_and_b, a_or_b, sum, extend_out},
54-
s: op ,
55-
o: r ,
54+
i_data: {a_and_b, a_or_b, sum, extend_out},
55+
i_sel : op ,
56+
o_data: r ,
5657
);
57-
/* verilator lint_off UNOPTFLAT */
5858
}

‎src/alu32.veryl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
// src/alu32.veryl
2+
13
module Alu32 (
24
a : input logic<32>,
35
b : input logic<32>,

‎src/arith.veryl‎

Lines changed: 3 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,11 @@ module Arith #(
1616
assign c = ca[msb];
1717

1818
for i in 0..Width :label {
19+
1920
var cl: logic;
21+
2022
assign cl = ca[i];
23+
2124
inst full_add: FullAdder (
2225
a : a[i] ,
2326
b : b[i] ^ sub,
@@ -26,73 +29,4 @@ module Arith #(
2629
carry: ca[i + 1] ,
2730
);
2831
}
29-
/* verilator lint_on UNOPTFLAT */
3032
}
31-
32-
#[test(arith)]
33-
embed (inline) sv{{{
34-
module test;
35-
logic [3:0] a;
36-
logic [3:0] b;
37-
logic sub;
38-
logic [3:0] r;
39-
logic v;
40-
logic c;
41-
42-
vips_Arith arith (a, b, sub, r, v, c);
43-
44-
initial begin
45-
a = 0; b = 0; sub = 0;
46-
#10;
47-
assert (r == 0 & v == 0 & c == 0) else $error("0+0");
48-
49-
a = 5; b = 2; sub = 0;
50-
#10;
51-
assert (r == 7 & v == 0 & c == 0) else $error("5+2");
52-
53-
a = 5; b = 3; sub = 0;
54-
#10;
55-
// 0111
56-
// 0101
57-
// 0011
58-
// 01000
59-
assert (r == 8 & v == 1 & c == 0) else $error("5+3, V ", r, " ", v, " ", c);
60-
61-
a = 5; b = 10; sub = 0;
62-
#10;
63-
// 0
64-
// 0101 5
65-
// 1010 -6
66-
// 01111
67-
assert (r == 15 & v == 0 & c == 0) else $error("5+10 ", r, " ", v, " ", c);
68-
69-
a = 5; b = 11; sub = 0;
70-
#10;
71-
// 111
72-
// 0101 5
73-
// 1011 -5
74-
// 10000
75-
assert (r == 0 & v == 0 & c == 1) else $error("5+11 ", r, " ", v, " ", c);
76-
77-
a = 5; b = 3; sub = 1;
78-
#10;
79-
assert (r == 2 & v == 0 & c == 1) else $error("5-3 C", r, " ", v, " ", c);
80-
81-
a = 5; b = 6; sub = 1;
82-
#10;
83-
assert (r == 15 & v == 0 & c == 0) else $error("5-6 C", r, " ", v, " ", c);
84-
85-
a = 5; b = -3; sub = 1;
86-
#10;
87-
88-
// 0111
89-
// 0101 5
90-
// 0011 (--3)
91-
// ----
92-
// 01000
93-
assert (r == 8 & v == 1 & c == 0) else $error("5-(-3) C", r, " ", v, " ", c);
94-
95-
$finish;
96-
end
97-
endmodule
98-
}}}

‎src/arith_test.veryl‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
1+
#[test(arith)]
2+
embed (inline) sv{{{
3+
module test;
4+
/* verilator lint_off UNOPTFLAT */
5+
6+
logic [3:0] a;
7+
logic [3:0] b;
8+
logic sub;
9+
logic [3:0] r;
10+
logic v;
11+
logic c;
12+
13+
vips_Arith arith (a, b, sub, r, v, c);
14+
15+
initial begin
16+
a = 0; b = 0; sub = 0;
17+
#10;
18+
assert (r == 0 & v == 0 & c == 0) else $error("0+0");
19+
20+
a = 5; b = 2; sub = 0;
21+
#10;
22+
assert (r == 7 & v == 0 & c == 0) else $error("5+2");
23+
24+
a = 5; b = 3; sub = 0;
25+
#10;
26+
// 0111
27+
// 0101
28+
// 0011
29+
// 01000
30+
assert (r == 8 & v == 1 & c == 0) else $error("5+3, V ", r, " ", v, " ", c);
31+
32+
a = 5; b = 10; sub = 0;
33+
#10;
34+
// 0
35+
// 0101 5
36+
// 1010 -6
37+
// 01111
38+
assert (r == 15 & v == 0 & c == 0) else $error("5+10 ", r, " ", v, " ", c);
39+
40+
a = 5; b = 11; sub = 0;
41+
#10;
42+
// 111
43+
// 0101 5
44+
// 1011 -5
45+
// 10000
46+
assert (r == 0 & v == 0 & c == 1) else $error("5+11 ", r, " ", v, " ", c);
47+
48+
a = 5; b = 3; sub = 1;
49+
#10;
50+
assert (r == 2 & v == 0 & c == 1) else $error("5-3 C", r, " ", v, " ", c);
51+
52+
a = 5; b = 6; sub = 1;
53+
#10;
54+
assert (r == 15 & v == 0 & c == 0) else $error("5-6 C", r, " ", v, " ", c);
55+
56+
a = 5; b = -3; sub = 1;
57+
#10;
58+
59+
// 0111
60+
// 0101 5
61+
// 0011 (--3)
62+
// ----
63+
// 01000
64+
assert (r == 8 & v == 1 & c == 0) else $error("5-(-3) C", r, " ", v, " ", c);
65+
66+
$finish;
67+
end
68+
endmodule
69+
}}}

‎src/decoder.veryl‎

Lines changed: 1 addition & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ module Decoder (
7474
sign_extend = 1;
7575
alu_source = 1;
7676
alu_sub = 1;
77-
alu_op = 2'b10;
77+
alu_op = 2'b11;
7878
}
7979
// R-type
8080
6'b00_0000: {
@@ -206,51 +206,3 @@ embed (inline) sv{{{
206206
end
207207
endmodule
208208
}}}
209-
210-
211-
// logic [31:0] addr;
212-
// logic [31:0] instr;
213-
214-
// vips_InstrMem instr_mem(addr, instr);
215-
216-
217-
// case opcode {
218-
// // andi, ori, addi, slti
219-
// 6'b00_1100 | 6'b00_1101 | 6'b00_1000 | 6'b00_1010: {
220-
// write_enable = 1;
221-
// sign_extend = !opcode[2];
222-
// alu_source = 1;
223-
// alu_op = case opcode {
224-
// // andi
225-
// 6'b00_1100: 'b00,
226-
// // ori
227-
// 6'b00_1101: 'b01,
228-
// // addi
229-
// 6'b00_1000: 'b10,
230-
// // slti
231-
// 6'b00_1010: 'b11,
232-
// default : 0,
233-
234-
// };
235-
// }
236-
// default: {}
237-
// }
238-
239-
// sequentially assigned variables
240-
// var v_we : logic;
241-
// var v_sign_ext: logic;
242-
// var v_alu_src : logic;
243-
// var v_alu_sub : logic;
244-
// var v_alu_op : logic;
245-
246-
// write_enable = v_we;
247-
// alu_source = v_alu_src;
248-
// alu_sub = v_alu_sub;
249-
// alu_op = v_alu_op;
250-
251-
// // default assignments
252-
// v_we = 0;
253-
// v_sign_ext = 0; // zero extend
254-
// v_alu_src = 0; // R type
255-
// v_alu_sub = 0; // add
256-
// v_alu_op = 0; // and

‎src/full_adder.veryl‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
1-
module FullAdder #() (
1+
// src/full_adder.veryl
2+
3+
module FullAdder (
24
a : input logic,
35
b : input logic,
46
c : input logic,

‎src/instr_mem.veryl‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -5,19 +5,19 @@ module InstrMem (
55
o_instr: output logic<32>,
66
) {
77
assign o_instr = case i_addr {
8-
32'h0000_0000: 32'b001000_00001_00000_0000000000000100, // addi zero at 4, (nop)
9-
32'h0000_0004: 32'b001000_00001_00000_1111111111111000, // addi zero at -8, (nop)
10-
32'h0000_0008: 32'b001000_00010_00001_0000000000001000, // addi r1 r2 8, (r1 <- 8)
11-
32'h0000_000c: 32'b000000_00000_00001_00010_00000_100000, // add r2 zero r1 (r2 <- 8)
12-
32'h0000_0010: 32'b001000_00000_00010_0000000000000010, // addi r2 zero 2 (r2 <- 2)
13-
32'h0000_0014: 32'b000000_00010_00001_00011_00000_100010, // sub r3 r2 r1 (r3 <- 2 - 8 = -6)
14-
32'h0000_0018: 32'b000000_00000_00011_00100_00000_101010, // slt r4 zero v1 (r4 <- zero < (-6) = 0)
15-
32'h0000_001c: 32'b001010_00011_00100_1111111111111011, // slti r4 v1 -5 (r4 <- (-6) < (-5) = 1)
16-
32'h0000_0020: 32'b000000_00000_00100_00101_00000_101010, // slt r5 zero r1 (r5 <- 0 < 8 = 1)
17-
32'h0000_0024: 32'b000000_00011_00000_00110_00000_100101, // or r6 r3 zero (r6 <- -6 | 0 = -6)
18-
32'h0000_0028: 32'b000000_00001_00011_00111_00000_100100, // and r7 r1 r3 (r7 <- b0..1000 & b1..1010 = b1000 )
19-
32'h0000_002c: 32'b000000_00001_00011_01000_00000_100111, // nor a4 at v1 (-- not supported --)
20-
default : 32'b111111_00001_00000_0000000000000001, // lui zero 1 (-- not supported --)
8+
32'h0000_0000: 32'b001000_00001_00000_0000000000000100, // 00 addi zero at 4, (nop)
9+
32'h0000_0004: 32'b001000_00001_00000_1111111111111000, // 04 addi zero at -8, (nop)
10+
32'h0000_0008: 32'b001000_00010_00001_0000000000001000, // 08 addi r1 r2 8, (r1 <- 8)
11+
32'h0000_000c: 32'b000000_00000_00001_00010_00000_100000, // 0c add r2 zero r1 (r2 <- 8)
12+
32'h0000_0010: 32'b001000_00000_00010_0000000000000010, // 10 addi r2 zero 2 (r2 <- 2)
13+
32'h0000_0014: 32'b000000_00010_00001_00011_00000_100010, // 14 sub r3 r2 r1 (r3 <- 2 - 8 = -6)
14+
32'h0000_0018: 32'b000000_00000_00011_00100_00000_101010, // 18 slt r4 zero v1 (r4 <- zero < (-6) = 0)
15+
32'h0000_001c: 32'b001010_00011_00100_1111111111111011, // 1c slti r4 v1 -5 (r4 <- (-6) < (-5) = 1)
16+
32'h0000_0020: 32'b000000_00000_00100_00101_00000_101010, // 20 slt r5 zero r1 (r5 <- 0 < 8 = 1)
17+
32'h0000_0024: 32'b000000_00011_00000_00110_00000_100101, // 24 or r6 r3 zero (r6 <- -6 | 0 = -6)
18+
32'h0000_0028: 32'b000000_00001_00011_00111_00000_100100, // 28 and r7 r1 r3 (r7 <- b0..1000 & b1..1010 = b1000 )
19+
32'h0000_002c: 32'b000000_00001_00011_01000_00000_100111, // 2c nor a4 at v1 (-- not supported --)
20+
default : 32'b111111_00001_00000_0000000000000001, // 30 lui zero 1 (-- not supported --)
2121
};
2222
}
2323

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