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Move to Vips1 for 1st version
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‎src/vips1.veryl‎

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// src/vips1.veryl
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module Vips1 (
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i_clk : input clock ,
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i_reset : input reset_async_high ,
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i_dbg_reg : input logic <5> ,
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o_dbg_reg_data: output logic <32>,
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) {
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var pc_addr: logic<32>;
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inst pcplus4: PcPlus4 (
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i_clk ,
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i_reset ,
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o_pc : pc_addr,
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);
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var instr: logic<32>;
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inst instr_mem: InstrMem (
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i_addr : pc_addr,
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o_instr: instr ,
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);
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let opcode: logic<6> = instr[31:26];
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let funct : logic<6> = instr[5:0];
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let rs : logic<5> = instr[25:21];
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let rt : logic<5> = instr[20:16];
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let rd : logic<5> = instr[15:11];
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let imm : logic<16> = instr[15:0];
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var reg_destination: logic ;
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var z : logic ;
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var write_enable : logic ;
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var sign_extend : logic ;
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var alu_source : logic ;
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var alu_sub : logic ;
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var alu_op : logic<2>;
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inst decoder: Decoder (
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opcode ,
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funct ,
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z ,
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reg_destination ,
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write_enable ,
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sign_extend ,
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alu_source ,
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alu_sub ,
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alu_op ,
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);
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var wb_reg: logic<5>;
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inst reg_d_mux: Mux2 #(
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Width: 5,
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) (
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i_data: {rt, rd} ,
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i_sel : reg_destination,
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o_data: wb_reg ,
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);
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var a_data: logic<32>;
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var b_data: logic<32>;
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var w_data: logic<32>;
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inst regfile: RegFile (
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i_clk ,
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i_reset ,
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i_a_addr : rs ,
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i_b_addr : rt ,
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i_w_ena : write_enable ,
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i_w_addr : wb_reg ,
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i_w_data : w_data ,
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i_dbg_addr: i_dbg_reg ,
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o_a_data : a_data ,
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o_b_data : b_data ,
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o_dbg_data: o_dbg_reg_data,
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);
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var imm32ext: logic<32>;
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inst extend16to32: Extend16to32 (
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i_data : imm ,
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i_sign_ext: sign_extend,
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o_data : imm32ext ,
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);
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var alu_src: logic<32>;
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inst alu_src_mux: Mux2 (
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i_data: {b_data, imm32ext},
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i_sel : alu_source ,
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o_data: alu_src ,
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);
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var v: logic;
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var c: logic;
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inst alu: Alu (
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a : a_data ,
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b : alu_src,
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sub: alu_sub,
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op : alu_op ,
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r : w_data ,
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v ,
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c ,
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z ,
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);
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}
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#[test(vips1)]
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embed (inline) sv{{{
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module test;
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logic i_clk;
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logic i_reset;
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logic [4:0] i_dbg_reg;
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logic [31:0] o_dbg_reg_data;
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vips_Vips1 vips(i_clk, i_reset, i_dbg_reg, o_dbg_reg_data);
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task clock;
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begin
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i_clk = 0; #10; i_clk = 1; #10;
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end
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endtask
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initial begin
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i_reset = 1;
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clock(); // 00 addi zero at 4, (nop)
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assert (vips.pc_addr == 32'h00);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 1);
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assert (vips.alu_op == 2'b10);
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assert (vips.alu_sub == 0);
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assert (vips.sign_extend == 1);
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assert (vips.reg_destination == 0);
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i_reset = 0;
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clock(); // 04 addi zero at -8, (nop)
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assert (vips.pc_addr == 32'h04);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 1);
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assert (vips.alu_op == 2'b10);
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assert (vips.alu_sub == 0);
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assert (vips.sign_extend == 1);
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assert (vips.reg_destination == 0);
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clock(); // 08 addi r1 r2 8, (r1 <- 8)
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assert (vips.pc_addr == 32'h08);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 1);
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assert (vips.alu_op == 2'b10);
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assert (vips.alu_sub == 0);
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assert (vips.sign_extend == 1);
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assert (vips.reg_destination == 0);
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clock(); // 0c add r2 zero r1 (r2 <- 8)
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assert (vips.pc_addr == 32'h0c);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 0);
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assert (vips.alu_op == 2'b10);
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assert (vips.alu_sub == 0);
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assert (vips.sign_extend == 0); // don't care
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assert (vips.reg_destination == 1);
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clock(); // 10 addi r2 zero 2 (r2 <- 2)
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assert (vips.pc_addr == 32'h10);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 1);
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assert (vips.alu_op == 2'b10);
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assert (vips.alu_sub == 0);
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assert (vips.sign_extend == 1);
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assert (vips.reg_destination == 0);
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clock(); // 14 sub r3 r2 r1 (r3 <- 2 - 8 = -6)
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assert (vips.pc_addr == 32'h14);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 0);
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assert (vips.alu_op == 2'b10);
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assert (vips.alu_sub == 1);
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assert (vips.sign_extend == 0); // don't care
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assert (vips.reg_destination == 1);
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clock(); // 18 slt r4 zero v1 (r4 <- zero < (-6) = 0)
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assert (vips.pc_addr == 32'h18);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 0);
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assert (vips.alu_op == 2'b11);
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assert (vips.alu_sub == 1);
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assert (vips.sign_extend == 0); // don't care
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assert (vips.reg_destination == 1);
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clock(); // 1c slti r4 v1 -5 (r4 <- (-6) < (-5) = 1)
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assert (vips.pc_addr == 32'h1c);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 1);
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assert (vips.alu_op == 2'b11);
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assert (vips.alu_sub == 1);
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assert (vips.sign_extend == 1);
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assert (vips.reg_destination == 0);
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clock(); // 20 slt r5 zero r1 (r5 <- 0 < 8 = 1)
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assert (vips.pc_addr == 32'h20);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 0);
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assert (vips.alu_op == 2'b11);
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assert (vips.alu_sub == 1);
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assert (vips.sign_extend == 0); // don't care
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assert (vips.reg_destination == 1);
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clock(); // 24 or r6 r3 zero (r6 <- -6 | 0 = -6)
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assert (vips.pc_addr == 32'h24);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 0);
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assert (vips.alu_op == 2'b01);
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assert (vips.alu_sub == 0);
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assert (vips.sign_extend == 0);
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assert (vips.reg_destination == 1);
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clock(); // 28 and r7 r1 r3 (r7 <- b0..1000 & b1..1010 = b1000 )
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assert (vips.pc_addr == 32'h28);
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assert (vips.write_enable == 1);
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assert (vips.alu_source == 0);
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assert (vips.alu_op == 2'b00);
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assert (vips.alu_sub == 0); // don't care
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assert (vips.sign_extend == 0);
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assert (vips.reg_destination == 1);
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clock(); // 2c nor a4 at v1 (-- not supported --)
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assert (vips.pc_addr == 32'h2c);
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assert (vips.write_enable == 0);
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assert (vips.alu_source == 0); // don't care
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assert (vips.alu_sub == 0); // don't care
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assert (vips.sign_extend == 0); // don't care
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assert (vips.reg_destination == 1); // don't care
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clock(); // 30 lui zero 1 (-- not supported --)
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assert (vips.pc_addr == 32'h30);
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assert (vips.write_enable == 0);
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assert (vips.alu_source == 0); // don't care
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assert (vips.alu_sub == 0); // don't care
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assert (vips.sign_extend == 0); // don't care
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assert (vips.reg_destination == 0); // don't care
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$finish;
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end
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endmodule
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}}}

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