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codegenlegacy.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.
/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX CodeGenerator XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#include "codegen.h"
#ifdef LEGACY_BACKEND // This file is NOT used for the '!LEGACY_BACKEND' that uses the linear scan register allocator
#ifdef _TARGET_AMD64_
#error AMD64 must be !LEGACY_BACKEND
#endif
#ifdef _TARGET_ARM64_
#error ARM64 must be !LEGACY_BACKEND
#endif
#include "gcinfo.h"
#include "emit.h"
#ifndef JIT32_GCENCODER
#include "gcinfoencoder.h"
#endif
/*****************************************************************************
*
* Determine what variables die between beforeSet and afterSet, and
* update the liveness globals accordingly:
* compiler->compCurLife, gcInfo.gcVarPtrSetCur, regSet.rsMaskVars, gcInfo.gcRegGCrefSetCur, gcInfo.gcRegByrefSetCur
*/
void CodeGen::genDyingVars(VARSET_VALARG_TP beforeSet, VARSET_VALARG_TP afterSet)
{
unsigned varNum;
LclVarDsc* varDsc;
regMaskTP regBit;
VARSET_TP VARSET_INIT_NOCOPY(deadSet, VarSetOps::Diff(compiler, beforeSet, afterSet));
if (VarSetOps::IsEmpty(compiler, deadSet))
return;
/* iterate through the dead variables */
VARSET_ITER_INIT(compiler, iter, deadSet, varIndex);
while (iter.NextElem(compiler, &varIndex))
{
varNum = compiler->lvaTrackedToVarNum[varIndex];
varDsc = compiler->lvaTable + varNum;
/* Remove this variable from the 'deadSet' bit set */
noway_assert(VarSetOps::IsMember(compiler, compiler->compCurLife, varIndex));
VarSetOps::RemoveElemD(compiler, compiler->compCurLife, varIndex);
noway_assert(!VarSetOps::IsMember(compiler, gcInfo.gcTrkStkPtrLcls, varIndex) ||
VarSetOps::IsMember(compiler, gcInfo.gcVarPtrSetCur, varIndex));
VarSetOps::RemoveElemD(compiler, gcInfo.gcVarPtrSetCur, varIndex);
/* We are done if the variable is not enregistered */
if (!varDsc->lvRegister)
{
#ifdef DEBUG
if (compiler->verbose)
{
printf("\t\t\t\t\t\t\tV%02u,T%02u is a dyingVar\n", varNum, varDsc->lvVarIndex);
}
#endif
continue;
}
#if !FEATURE_FP_REGALLOC
// We don't do FP-enreg of vars whose liveness changes in GTF_COLON_COND
if (!varDsc->IsFloatRegType())
#endif
{
/* Get hold of the appropriate register bit(s) */
if (varTypeIsFloating(varDsc->TypeGet()))
{
regBit = genRegMaskFloat(varDsc->lvRegNum, varDsc->TypeGet());
}
else
{
regBit = genRegMask(varDsc->lvRegNum);
if (isRegPairType(varDsc->lvType) && varDsc->lvOtherReg != REG_STK)
regBit |= genRegMask(varDsc->lvOtherReg);
}
#ifdef DEBUG
if (compiler->verbose)
{
printf("\t\t\t\t\t\t\tV%02u,T%02u in reg %s is a dyingVar\n", varNum, varDsc->lvVarIndex,
compiler->compRegVarName(varDsc->lvRegNum));
}
#endif
noway_assert((regSet.rsMaskVars & regBit) != 0);
regSet.RemoveMaskVars(regBit);
// Remove GC tracking if any for this register
if ((regBit & regSet.rsMaskUsed) == 0) // The register may be multi-used
gcInfo.gcMarkRegSetNpt(regBit);
}
}
}
/*****************************************************************************
*
* Change the given enregistered local variable node to a register variable node
*/
void CodeGenInterface::genBashLclVar(GenTreePtr tree, unsigned varNum, LclVarDsc* varDsc)
{
noway_assert(tree->gtOper == GT_LCL_VAR);
noway_assert(varDsc->lvRegister);
if (isRegPairType(varDsc->lvType))
{
/* Check for the case of a variable that was narrowed to an int */
if (isRegPairType(tree->gtType))
{
genMarkTreeInRegPair(tree, gen2regs2pair(varDsc->lvRegNum, varDsc->lvOtherReg));
return;
}
noway_assert(tree->gtFlags & GTF_VAR_CAST);
noway_assert(tree->gtType == TYP_INT);
}
else
{
noway_assert(!isRegPairType(tree->gtType));
}
/* It's a register variable -- modify the node */
unsigned livenessFlags = (tree->gtFlags & GTF_LIVENESS_MASK);
ValueNumPair vnp = tree->gtVNPair; // Save the ValueNumPair
tree->SetOper(GT_REG_VAR);
tree->gtVNPair = vnp; // Preserve the ValueNumPair, as SetOper will clear it.
tree->gtFlags |= livenessFlags;
tree->gtFlags |= GTF_REG_VAL;
tree->gtRegNum = varDsc->lvRegNum;
tree->gtRegVar.gtRegNum = varDsc->lvRegNum;
tree->gtRegVar.SetLclNum(varNum);
}
// inline
void CodeGen::saveLiveness(genLivenessSet* ls)
{
VarSetOps::Assign(compiler, ls->liveSet, compiler->compCurLife);
VarSetOps::Assign(compiler, ls->varPtrSet, gcInfo.gcVarPtrSetCur);
ls->maskVars = (regMaskSmall)regSet.rsMaskVars;
ls->gcRefRegs = (regMaskSmall)gcInfo.gcRegGCrefSetCur;
ls->byRefRegs = (regMaskSmall)gcInfo.gcRegByrefSetCur;
}
// inline
void CodeGen::restoreLiveness(genLivenessSet* ls)
{
VarSetOps::Assign(compiler, compiler->compCurLife, ls->liveSet);
VarSetOps::Assign(compiler, gcInfo.gcVarPtrSetCur, ls->varPtrSet);
regSet.rsMaskVars = ls->maskVars;
gcInfo.gcRegGCrefSetCur = ls->gcRefRegs;
gcInfo.gcRegByrefSetCur = ls->byRefRegs;
}
// inline
void CodeGen::checkLiveness(genLivenessSet* ls)
{
assert(VarSetOps::Equal(compiler, compiler->compCurLife, ls->liveSet));
assert(VarSetOps::Equal(compiler, gcInfo.gcVarPtrSetCur, ls->varPtrSet));
assert(regSet.rsMaskVars == ls->maskVars);
assert(gcInfo.gcRegGCrefSetCur == ls->gcRefRegs);
assert(gcInfo.gcRegByrefSetCur == ls->byRefRegs);
}
// inline
bool CodeGenInterface::genMarkLclVar(GenTreePtr tree)
{
unsigned varNum;
LclVarDsc* varDsc;
assert(tree->gtOper == GT_LCL_VAR);
/* Does the variable live in a register? */
varNum = tree->gtLclVarCommon.gtLclNum;
assert(varNum < compiler->lvaCount);
varDsc = compiler->lvaTable + varNum;
if (varDsc->lvRegister)
{
genBashLclVar(tree, varNum, varDsc);
return true;
}
else
{
return false;
}
}
// inline
GenTreePtr CodeGen::genGetAddrModeBase(GenTreePtr tree)
{
bool rev;
unsigned mul;
unsigned cns;
GenTreePtr adr;
GenTreePtr idx;
if (genCreateAddrMode(tree, // address
0, // mode
false, // fold
RBM_NONE, // reg mask
&rev, // reverse ops
&adr, // base addr
&idx, // index val
#if SCALED_ADDR_MODES
&mul, // scaling
#endif
&cns, // displacement
true)) // don't generate code
return adr;
else
return NULL;
}
// inline
void CodeGen::genSinglePush()
{
genStackLevel += sizeof(void*);
}
// inline
void CodeGen::genSinglePop()
{
genStackLevel -= sizeof(void*);
}
#if FEATURE_STACK_FP_X87
// inline
void CodeGenInterface::genResetFPstkLevel(unsigned newValue /* = 0 */)
{
genFPstkLevel = newValue;
}
// inline
unsigned CodeGenInterface::genGetFPstkLevel()
{
return genFPstkLevel;
}
// inline
void CodeGenInterface::genIncrementFPstkLevel(unsigned inc /* = 1 */)
{
noway_assert((inc == 0) || genFPstkLevel + inc > genFPstkLevel);
genFPstkLevel += inc;
}
// inline
void CodeGenInterface::genDecrementFPstkLevel(unsigned dec /* = 1 */)
{
noway_assert((dec == 0) || genFPstkLevel - dec < genFPstkLevel);
genFPstkLevel -= dec;
}
#endif // FEATURE_STACK_FP_X87
/*****************************************************************************
*
* Generate code that will set the given register to the integer constant.
*/
void CodeGen::genSetRegToIcon(regNumber reg, ssize_t val, var_types type, insFlags flags)
{
noway_assert(type != TYP_REF || val == NULL);
/* Does the reg already hold this constant? */
if (!regTracker.rsIconIsInReg(val, reg))
{
if (val == 0)
{
instGen_Set_Reg_To_Zero(emitActualTypeSize(type), reg, flags);
}
#ifdef _TARGET_ARM_
// If we can set a register to a constant with a small encoding, then do that.
else if (arm_Valid_Imm_For_Small_Mov(reg, val, flags))
{
instGen_Set_Reg_To_Imm(emitActualTypeSize(type), reg, val, flags);
}
#endif
else
{
/* See if a register holds the value or a close value? */
bool constantLoaded = false;
ssize_t delta;
regNumber srcReg = regTracker.rsIconIsInReg(val, &delta);
if (srcReg != REG_NA)
{
if (delta == 0)
{
inst_RV_RV(INS_mov, reg, srcReg, type, emitActualTypeSize(type), flags);
constantLoaded = true;
}
else
{
#if defined(_TARGET_XARCH_)
/* delta should fit inside a byte */
if (delta == (signed char)delta)
{
/* use an lea instruction to set reg */
getEmitter()->emitIns_R_AR(INS_lea, emitTypeSize(type), reg, srcReg, (int)delta);
constantLoaded = true;
}
#elif defined(_TARGET_ARM_)
/* We found a register 'regS' that has the value we need, modulo a small delta.
That is, the value we need is 'regS + delta'.
We one to generate one of the following instructions, listed in order of preference:
adds regD, delta ; 2 bytes. if regD == regS, regD is a low register, and
0<=delta<=255
subs regD, delta ; 2 bytes. if regD == regS, regD is a low register, and
-255<=delta<=0
adds regD, regS, delta ; 2 bytes. if regD and regS are low registers and 0<=delta<=7
subs regD, regS, delta ; 2 bytes. if regD and regS are low registers and -7<=delta<=0
mov regD, icon ; 4 bytes. icon is a wacky Thumb 12-bit immediate.
movw regD, icon ; 4 bytes. 0<=icon<=65535
add.w regD, regS, delta ; 4 bytes. delta is a wacky Thumb 12-bit immediate.
sub.w regD, regS, delta ; 4 bytes. delta is a wacky Thumb 12-bit immediate.
addw regD, regS, delta ; 4 bytes. 0<=delta<=4095
subw regD, regS, delta ; 4 bytes. -4095<=delta<=0
If it wasn't for the desire to generate the "mov reg,icon" forms if possible (and no bigger
than necessary), this would be a lot simpler. Note that we might set the overflow flag: we
can have regS containing the largest signed int 0x7fffffff and need the smallest signed int
0x80000000. In this case, delta will be 1.
*/
bool useAdd = false;
regMaskTP regMask = genRegMask(reg);
regMaskTP srcRegMask = genRegMask(srcReg);
if ((flags != INS_FLAGS_NOT_SET) && (reg == srcReg) && (regMask & RBM_LOW_REGS) &&
(unsigned_abs(delta) <= 255))
{
useAdd = true;
}
else if ((flags != INS_FLAGS_NOT_SET) && (regMask & RBM_LOW_REGS) && (srcRegMask & RBM_LOW_REGS) &&
(unsigned_abs(delta) <= 7))
{
useAdd = true;
}
else if (arm_Valid_Imm_For_Mov(val))
{
// fall through to general "!constantLoaded" case below
}
else if (arm_Valid_Imm_For_Add(delta, flags))
{
useAdd = true;
}
if (useAdd)
{
getEmitter()->emitIns_R_R_I(INS_add, EA_4BYTE, reg, srcReg, delta, flags);
constantLoaded = true;
}
#else
assert(!"Codegen missing");
#endif
}
}
if (!constantLoaded) // Have we loaded it yet?
{
#ifdef _TARGET_X86_
if (val == -1)
{
/* or reg,-1 takes 3 bytes */
inst_RV_IV(INS_OR, reg, val, emitActualTypeSize(type));
}
else
/* For SMALL_CODE it is smaller to push a small immediate and
then pop it into the dest register */
if ((compiler->compCodeOpt() == Compiler::SMALL_CODE) && val == (signed char)val)
{
/* "mov" has no s(sign)-bit and so always takes 6 bytes,
whereas push+pop takes 2+1 bytes */
inst_IV(INS_push, val);
genSinglePush();
inst_RV(INS_pop, reg, type);
genSinglePop();
}
else
#endif // _TARGET_X86_
{
instGen_Set_Reg_To_Imm(emitActualTypeSize(type), reg, val, flags);
}
}
}
}
regTracker.rsTrackRegIntCns(reg, val);
gcInfo.gcMarkRegPtrVal(reg, type);
}
/*****************************************************************************
*
* Find an existing register set to the given integer constant, or
* pick a register and generate code that will set it to the integer constant.
*
* If no existing register is set to the constant, it will use regSet.rsPickReg(regBest)
* to pick some register to set. NOTE that this means the returned regNumber
* might *not* be in regBest. It also implies that you should lock any registers
* you don't want spilled (not just mark as used).
*
*/
regNumber CodeGen::genGetRegSetToIcon(ssize_t val, regMaskTP regBest /* = 0 */, var_types type /* = TYP_INT */)
{
regNumber regCns;
#if REDUNDANT_LOAD
// Is there already a register with zero that we can use?
regCns = regTracker.rsIconIsInReg(val);
if (regCns == REG_NA)
#endif
{
// If not, grab a register to hold the constant, preferring
// any register besides RBM_TMP_0 so it can hopefully be re-used
regCns = regSet.rsPickReg(regBest, regBest & ~RBM_TMP_0);
// Now set the constant
genSetRegToIcon(regCns, val, type);
}
// NOTE: there is guarantee that regCns is in regBest's mask
return regCns;
}
/*****************************************************************************/
/*****************************************************************************
*
* Add the given constant to the specified register.
* 'tree' is the resulting tree
*/
void CodeGen::genIncRegBy(regNumber reg, ssize_t ival, GenTreePtr tree, var_types dstType, bool ovfl)
{
bool setFlags = (tree != NULL) && tree->gtSetFlags();
#ifdef _TARGET_XARCH_
/* First check to see if we can generate inc or dec instruction(s) */
/* But avoid inc/dec on P4 in general for fast code or inside loops for blended code */
if (!ovfl && !compiler->optAvoidIncDec(compiler->compCurBB->getBBWeight(compiler)))
{
emitAttr size = emitTypeSize(dstType);
switch (ival)
{
case 2:
inst_RV(INS_inc, reg, dstType, size);
__fallthrough;
case 1:
inst_RV(INS_inc, reg, dstType, size);
goto UPDATE_LIVENESS;
case -2:
inst_RV(INS_dec, reg, dstType, size);
__fallthrough;
case -1:
inst_RV(INS_dec, reg, dstType, size);
goto UPDATE_LIVENESS;
}
}
#endif
insFlags flags = setFlags ? INS_FLAGS_SET : INS_FLAGS_DONT_CARE;
inst_RV_IV(INS_add, reg, ival, emitActualTypeSize(dstType), flags);
#ifdef _TARGET_XARCH_
UPDATE_LIVENESS:
#endif
if (setFlags)
genFlagsEqualToReg(tree, reg);
regTracker.rsTrackRegTrash(reg);
gcInfo.gcMarkRegSetNpt(genRegMask(reg));
if (tree != NULL)
{
if (!tree->OperIsAssignment())
{
genMarkTreeInReg(tree, reg);
if (varTypeIsGC(tree->TypeGet()))
gcInfo.gcMarkRegSetByref(genRegMask(reg));
}
}
}
/*****************************************************************************
*
* Subtract the given constant from the specified register.
* Should only be used for unsigned sub with overflow. Else
* genIncRegBy() can be used using -ival. We shouldn't use genIncRegBy()
* for these cases as the flags are set differently, and the following
* check for overflow won't work correctly.
* 'tree' is the resulting tree.
*/
void CodeGen::genDecRegBy(regNumber reg, ssize_t ival, GenTreePtr tree)
{
noway_assert((tree->gtFlags & GTF_OVERFLOW) &&
((tree->gtFlags & GTF_UNSIGNED) || ival == ((tree->gtType == TYP_INT) ? INT32_MIN : SSIZE_T_MIN)));
noway_assert(tree->gtType == TYP_INT || tree->gtType == TYP_I_IMPL);
regTracker.rsTrackRegTrash(reg);
noway_assert(!varTypeIsGC(tree->TypeGet()));
gcInfo.gcMarkRegSetNpt(genRegMask(reg));
insFlags flags = tree->gtSetFlags() ? INS_FLAGS_SET : INS_FLAGS_DONT_CARE;
inst_RV_IV(INS_sub, reg, ival, emitActualTypeSize(tree->TypeGet()), flags);
if (tree->gtSetFlags())
genFlagsEqualToReg(tree, reg);
if (tree)
{
genMarkTreeInReg(tree, reg);
}
}
/*****************************************************************************
*
* Multiply the specified register by the given value.
* 'tree' is the resulting tree
*/
void CodeGen::genMulRegBy(regNumber reg, ssize_t ival, GenTreePtr tree, var_types dstType, bool ovfl)
{
noway_assert(genActualType(dstType) == TYP_INT || genActualType(dstType) == TYP_I_IMPL);
regTracker.rsTrackRegTrash(reg);
if (tree)
{
genMarkTreeInReg(tree, reg);
}
bool use_shift = false;
unsigned shift_by = 0;
if ((dstType >= TYP_INT) && !ovfl && (ival > 0) && ((ival & (ival - 1)) == 0))
{
use_shift = true;
BitScanForwardPtr((ULONG*)&shift_by, (ULONG)ival);
}
if (use_shift)
{
if (shift_by != 0)
{
insFlags flags = tree->gtSetFlags() ? INS_FLAGS_SET : INS_FLAGS_DONT_CARE;
inst_RV_SH(INS_SHIFT_LEFT_LOGICAL, emitTypeSize(dstType), reg, shift_by, flags);
if (tree->gtSetFlags())
genFlagsEqualToReg(tree, reg);
}
}
else
{
instruction ins;
#ifdef _TARGET_XARCH_
ins = getEmitter()->inst3opImulForReg(reg);
#else
ins = INS_mul;
#endif
inst_RV_IV(ins, reg, ival, emitActualTypeSize(dstType));
}
}
/*****************************************************************************/
/*****************************************************************************/
/*****************************************************************************
*
* Compute the value 'tree' into a register that's in 'needReg'
* (or any free register if 'needReg' is RBM_NONE).
*
* Note that 'needReg' is just a recommendation unless mustReg==RegSet::EXACT_REG.
* If keepReg==RegSet::KEEP_REG, we mark the register as being used.
*
* If you require that the register returned is trashable, pass true for 'freeOnly'.
*/
void CodeGen::genComputeReg(
GenTreePtr tree, regMaskTP needReg, RegSet::ExactReg mustReg, RegSet::KeepReg keepReg, bool freeOnly)
{
noway_assert(tree->gtType != TYP_VOID);
regNumber reg;
regNumber rg2;
#if FEATURE_STACK_FP_X87
noway_assert(genActualType(tree->gtType) == TYP_INT || genActualType(tree->gtType) == TYP_I_IMPL ||
genActualType(tree->gtType) == TYP_REF || tree->gtType == TYP_BYREF);
#elif defined(_TARGET_ARM_)
noway_assert(genActualType(tree->gtType) == TYP_INT || genActualType(tree->gtType) == TYP_I_IMPL ||
genActualType(tree->gtType) == TYP_REF || tree->gtType == TYP_BYREF ||
genActualType(tree->gtType) == TYP_FLOAT || genActualType(tree->gtType) == TYP_DOUBLE ||
genActualType(tree->gtType) == TYP_STRUCT);
#else
noway_assert(genActualType(tree->gtType) == TYP_INT || genActualType(tree->gtType) == TYP_I_IMPL ||
genActualType(tree->gtType) == TYP_REF || tree->gtType == TYP_BYREF ||
genActualType(tree->gtType) == TYP_FLOAT || genActualType(tree->gtType) == TYP_DOUBLE);
#endif
/* Generate the value, hopefully into the right register */
genCodeForTree(tree, needReg);
noway_assert(tree->gtFlags & GTF_REG_VAL);
// There is a workaround in genCodeForTreeLng() that changes the type of the
// tree of a GT_MUL with 64 bit result to TYP_INT from TYP_LONG, then calls
// genComputeReg(). genCodeForTree(), above, will put the result in gtRegPair for ARM,
// or leave it in EAX/EDX for x86, but only set EAX as gtRegNum. There's no point
// running the rest of this code, because anything looking at gtRegNum on ARM or
// attempting to move from EAX/EDX will be wrong.
if ((tree->OperGet() == GT_MUL) && (tree->gtFlags & GTF_MUL_64RSLT))
goto REG_OK;
reg = tree->gtRegNum;
/* Did the value end up in an acceptable register? */
if ((mustReg == RegSet::EXACT_REG) && needReg && !(genRegMask(reg) & needReg))
{
/* Not good enough to satisfy the caller's orders */
if (varTypeIsFloating(tree))
{
RegSet::RegisterPreference pref(needReg, RBM_NONE);
rg2 = regSet.PickRegFloat(tree->TypeGet(), &pref);
}
else
{
rg2 = regSet.rsGrabReg(needReg);
}
}
else
{
/* Do we have to end up with a free register? */
if (!freeOnly)
goto REG_OK;
/* Did we luck out and the value got computed into an unused reg? */
if (genRegMask(reg) & regSet.rsRegMaskFree())
goto REG_OK;
/* Register already in use, so spill previous value */
if ((mustReg == RegSet::EXACT_REG) && needReg && (genRegMask(reg) & needReg))
{
rg2 = regSet.rsGrabReg(needReg);
if (rg2 == reg)
{
gcInfo.gcMarkRegPtrVal(reg, tree->TypeGet());
tree->gtRegNum = reg;
goto REG_OK;
}
}
else
{
/* OK, let's find a trashable home for the value */
regMaskTP rv1RegUsed;
regSet.rsLockReg(genRegMask(reg), &rv1RegUsed);
rg2 = regSet.rsPickReg(needReg);
regSet.rsUnlockReg(genRegMask(reg), rv1RegUsed);
}
}
noway_assert(reg != rg2);
/* Update the value in the target register */
regTracker.rsTrackRegCopy(rg2, reg);
inst_RV_RV(ins_Copy(tree->TypeGet()), rg2, reg, tree->TypeGet());
/* The value has been transferred to 'reg' */
if ((genRegMask(reg) & regSet.rsMaskUsed) == 0)
gcInfo.gcMarkRegSetNpt(genRegMask(reg));
gcInfo.gcMarkRegPtrVal(rg2, tree->TypeGet());
/* The value is now in an appropriate register */
tree->gtRegNum = rg2;
REG_OK:
/* Does the caller want us to mark the register as used? */
if (keepReg == RegSet::KEEP_REG)
{
/* In case we're computing a value into a register variable */
genUpdateLife(tree);
/* Mark the register as 'used' */
regSet.rsMarkRegUsed(tree);
}
}
/*****************************************************************************
*
* Same as genComputeReg(), the only difference being that the result is
* guaranteed to end up in a trashable register.
*/
// inline
void CodeGen::genCompIntoFreeReg(GenTreePtr tree, regMaskTP needReg, RegSet::KeepReg keepReg)
{
genComputeReg(tree, needReg, RegSet::ANY_REG, keepReg, true);
}
/*****************************************************************************
*
* The value 'tree' was earlier computed into a register; free up that
* register (but also make sure the value is presently in a register).
*/
void CodeGen::genReleaseReg(GenTreePtr tree)
{
if (tree->gtFlags & GTF_SPILLED)
{
/* The register has been spilled -- reload it */
regSet.rsUnspillReg(tree, 0, RegSet::FREE_REG);
return;
}
regSet.rsMarkRegFree(genRegMask(tree->gtRegNum));
}
/*****************************************************************************
*
* The value 'tree' was earlier computed into a register. Check whether that
* register has been spilled (and reload it if so), and if 'keepReg' is RegSet::FREE_REG,
* free the register. The caller shouldn't need to be setting GCness of the register
* where tree will be recovered to, so we disallow keepReg==RegSet::FREE_REG for GC type trees.
*/
void CodeGen::genRecoverReg(GenTreePtr tree, regMaskTP needReg, RegSet::KeepReg keepReg)
{
if (tree->gtFlags & GTF_SPILLED)
{
/* The register has been spilled -- reload it */
regSet.rsUnspillReg(tree, needReg, keepReg);
return;
}
else if (needReg && (needReg & genRegMask(tree->gtRegNum)) == 0)
{
/* We need the tree in another register. So move it there */
noway_assert(tree->gtFlags & GTF_REG_VAL);
regNumber oldReg = tree->gtRegNum;
/* Pick an acceptable register */
regNumber reg = regSet.rsGrabReg(needReg);
/* Copy the value */
inst_RV_RV(INS_mov, reg, oldReg, tree->TypeGet());
tree->gtRegNum = reg;
gcInfo.gcMarkRegPtrVal(tree);
regSet.rsMarkRegUsed(tree);
regSet.rsMarkRegFree(oldReg, tree);
regTracker.rsTrackRegCopy(reg, oldReg);
}
/* Free the register if the caller desired so */
if (keepReg == RegSet::FREE_REG)
{
regSet.rsMarkRegFree(genRegMask(tree->gtRegNum));
// Can't use RegSet::FREE_REG on a GC type
noway_assert(!varTypeIsGC(tree->gtType));
}
else
{
noway_assert(regSet.rsMaskUsed & genRegMask(tree->gtRegNum));
}
}
/*****************************************************************************
*
* Move one half of a register pair to its new regPair(half).
*/
// inline
void CodeGen::genMoveRegPairHalf(GenTreePtr tree, regNumber dst, regNumber src, int off)
{
if (src == REG_STK)
{
// handle long to unsigned long overflow casts
while (tree->gtOper == GT_CAST)
{
noway_assert(tree->gtType == TYP_LONG);
tree = tree->gtCast.CastOp();
}
noway_assert(tree->gtEffectiveVal()->gtOper == GT_LCL_VAR);
noway_assert(tree->gtType == TYP_LONG);
inst_RV_TT(ins_Load(TYP_INT), dst, tree, off);
regTracker.rsTrackRegTrash(dst);
}
else
{
regTracker.rsTrackRegCopy(dst, src);
inst_RV_RV(INS_mov, dst, src, TYP_INT);
}
}
/*****************************************************************************
*
* The given long value is in a register pair, but it's not an acceptable
* one. We have to move the value into a register pair in 'needReg' (if
* non-zero) or the pair 'newPair' (when 'newPair != REG_PAIR_NONE').
*
* Important note: if 'needReg' is non-zero, we assume the current pair
* has not been marked as free. If, OTOH, 'newPair' is specified, we
* assume that the current register pair is marked as used and free it.
*/
void CodeGen::genMoveRegPair(GenTreePtr tree, regMaskTP needReg, regPairNo newPair)
{
regPairNo oldPair;
regNumber oldLo;
regNumber oldHi;
regNumber newLo;
regNumber newHi;
/* Either a target set or a specific pair may be requested */
noway_assert((needReg != 0) != (newPair != REG_PAIR_NONE));
/* Get hold of the current pair */
oldPair = tree->gtRegPair;
noway_assert(oldPair != newPair);
/* Are we supposed to move to a specific pair? */
if (newPair != REG_PAIR_NONE)
{
regMaskTP oldMask = genRegPairMask(oldPair);
regMaskTP loMask = genRegMask(genRegPairLo(newPair));
regMaskTP hiMask = genRegMask(genRegPairHi(newPair));
regMaskTP overlap = oldMask & (loMask | hiMask);
/* First lock any registers that are in both pairs */
noway_assert((regSet.rsMaskUsed & overlap) == overlap);
noway_assert((regSet.rsMaskLock & overlap) == 0);
regSet.rsMaskLock |= overlap;
/* Make sure any additional registers we need are free */
if ((loMask & regSet.rsMaskUsed) != 0 && (loMask & oldMask) == 0)
{
regSet.rsGrabReg(loMask);
}
if ((hiMask & regSet.rsMaskUsed) != 0 && (hiMask & oldMask) == 0)
{
regSet.rsGrabReg(hiMask);
}
/* Unlock those registers we have temporarily locked */
noway_assert((regSet.rsMaskUsed & overlap) == overlap);
noway_assert((regSet.rsMaskLock & overlap) == overlap);
regSet.rsMaskLock -= overlap;
/* We can now free the old pair */
regSet.rsMarkRegFree(oldMask);
}
else
{
/* Pick the new pair based on the caller's stated preference */
newPair = regSet.rsGrabRegPair(needReg);
}
// If grabbed pair is the same as old one we're done
if (newPair == oldPair)
{
noway_assert((oldLo = genRegPairLo(oldPair), oldHi = genRegPairHi(oldPair), newLo = genRegPairLo(newPair),
newHi = genRegPairHi(newPair), newLo != REG_STK && newHi != REG_STK));
return;
}
/* Move the values from the old pair into the new one */
oldLo = genRegPairLo(oldPair);
oldHi = genRegPairHi(oldPair);
newLo = genRegPairLo(newPair);
newHi = genRegPairHi(newPair);
noway_assert(newLo != REG_STK && newHi != REG_STK);
/* Careful - the register pairs might overlap */
if (newLo == oldLo)
{
/* The low registers are identical, just move the upper half */
noway_assert(newHi != oldHi);
genMoveRegPairHalf(tree, newHi, oldHi, sizeof(int));
}
else
{
/* The low registers are different, are the upper ones the same? */
if (newHi == oldHi)
{
/* Just move the lower half, then */
genMoveRegPairHalf(tree, newLo, oldLo, 0);
}
else
{
/* Both sets are different - is there an overlap? */
if (newLo == oldHi)
{
/* Are high and low simply swapped ? */
if (newHi == oldLo)
{
#ifdef _TARGET_ARM_
/* Let's use XOR swap to reduce register pressure. */
inst_RV_RV(INS_eor, oldLo, oldHi);
inst_RV_RV(INS_eor, oldHi, oldLo);
inst_RV_RV(INS_eor, oldLo, oldHi);
#else
inst_RV_RV(INS_xchg, oldHi, oldLo);
#endif
regTracker.rsTrackRegSwap(oldHi, oldLo);
}
else
{
/* New lower == old higher, so move higher half first */
noway_assert(newHi != oldLo);
genMoveRegPairHalf(tree, newHi, oldHi, sizeof(int));
genMoveRegPairHalf(tree, newLo, oldLo, 0);
}
}
else
{
/* Move lower half first */
genMoveRegPairHalf(tree, newLo, oldLo, 0);
genMoveRegPairHalf(tree, newHi, oldHi, sizeof(int));