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pConstpConst
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Added fifo combiner
1 parent b8af169 commit f7c4995

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lines changed

‎fifo_combiner.sv

+174
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//------------------------------------------------------------------------------
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// fifo_combiner.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, [email protected]
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Combines / accumulates data words from multiple FIFOs to a single output FIFO.
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// Features three different element enumeration strategies.
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// Reads if ANY input FIFO has data.
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//
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// See also fifo_operator.sv
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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fifo_combiner #(
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.WIDTH( 2 ),
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.ENCODER_MODE( "ROUND_ROBIN" ),
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.FWFT_MODE( "TRUE" ),
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.DATA_W( 32 )
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) FC1 (
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.clk( ),
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.nrst( ),
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.r_empty( ),
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.r_req( ),
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.r_data( ),
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.w_full( ), // connect to "almost_full" if FWFT_MODE="FALSE"
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.w_req( ),
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.w_data( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module fifo_combiner #( parameter
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WIDTH = 2, // number of input fifo ports to combine
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WIDTH_W = clogb2(WIDTH), // input port index width
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ENCODER_MODE = "ROUND_ROBIN", // "ROUND_ROBIN", "ROUND_ROBIN_PERFORMANCE" or "PRIORITY"
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FWFT_MODE = "TRUE", // "TRUE" - first word fall-trrough" mode
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// "FALSE" - normal fifo mode
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DATA_W = 32 // data field width
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)(
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input clk, // clock
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input nrst, // inverted reset
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// input ports
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input [WIDTH-1:0] r_empty,
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output [WIDTH-1:0] r_req,
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input [WIDTH-1:0][DATA_W-1:0] r_data,
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// output port
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input w_full,
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output logic w_req,
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output logic [DATA_W-1:0] w_data
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);
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logic enc_valid;
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logic [WIDTH-1:0] enc_filt;
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logic [WIDTH_W-1:0] enc_bin;
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logic [WIDTH-1:0] r_empty_rev;
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reverse_vector #(
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.WIDTH( WIDTH ) // WIDTH must be >=2
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) empty_rev (
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.in( r_empty[WIDTH-1:0] ),
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.out( r_empty_rev[WIDTH-1:0] )
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);
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generate
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if( ENCODER_MODE == "ROUND_ROBIN" ) begin
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round_robin_enc #(
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.WIDTH( WIDTH )
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) rr_enc (
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.clk( clk ),
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.nrst( nrst ),
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.id( ~r_empty[WIDTH-1:0] ),
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.od_valid( enc_valid ),
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.od_filt( enc_filt[WIDTH-1:0] ),
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.od_bin( enc_bin[WIDTH_W-1:0] )
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);
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end else if( ENCODER_MODE == "ROUND_ROBIN_PERFORMANCE" ) begin
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round_robin_performance_enc #(
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.WIDTH( WIDTH )
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) rr_perf_enc (
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.clk( clk ), // !!
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.nrst( nrst ),
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.id(~r_empty[WIDTH-1:0] ),
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.od_valid( enc_valid ),
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.od_filt( enc_filt[WIDTH-1:0] ),
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.od_bin( enc_bin[WIDTH_W-1:0] )
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);
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end else if( ENCODER_MODE == "PRIORITY" ) begin
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priority_enc #(
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.WIDTH( WIDTH ) // WIDTH must be >=2
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) pri_enc (
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.id( ~r_empty[WIDTH-1:0] ),
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.od_valid( enc_valid ),
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.od_filt( enc_filt[WIDTH-1:0] ),
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.od_bin( enc_bin[WIDTH_W-1:0] )
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);
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end // ENCODER_MODE
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endgenerate
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logic r_valid;
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assign r_valid = enc_valid && ~w_full;
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assign r_req[WIDTH-1:0] = {WIDTH{r_valid}} &&
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enc_filt[WIDTH-1:0];
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// buffering read data
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logic r_valid_d1 = 1'b0;
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logic [WIDTH_W-1:0] enc_bin_d1;
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logic [WIDTH-1:0][DATA_W-1:0] r_data_d1 = '0;
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always_ff @(posedge clk) begin
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if ( ~nrst ) begin
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r_valid_d1 <= 1'b0;
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enc_bin_d1[WIDTH_W-1:0] <= '0;
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r_data_d1[WIDTH-1:0] <= '0;
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end else begin
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r_valid_d1 <= r_valid;
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enc_bin_d1[WIDTH_W-1:0] <= enc_bin[WIDTH_W-1:0];
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r_data_d1[WIDTH-1:0] <= r_data[WIDTH-1:0];
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end
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end
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// routing data to write port
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generate
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if( FWFT_MODE == "TRUE" ) begin
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always_comb begin
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if ( ~nrst ) begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end else begin
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if( r_valid ) begin
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w_req = 1'b1;
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w_data[DATA_W-1:0] = r_data[enc_bin[WIDTH_W-1:0]][DATA_W-1:0];
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end else begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end
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end
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end
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end else if( FWFT_MODE == "FALSE" ) begin
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always_comb begin
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if ( ~nrst ) begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end else begin
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if( r_valid_d1 ) begin
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w_req = 1'b1;
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w_data[DATA_W-1:0] = r_data_d1[enc_bin_d1[WIDTH_W-1:0]][DATA_W-1:0];
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end else begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end
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end
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end
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end // FWFT_MODE
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endgenerate
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`include "clogb2.svh"
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endmodule
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‎fifo_operator.sv

+132
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//------------------------------------------------------------------------------
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// fifo_operator.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, [email protected]
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Performs custom operation on data words from multiple FIFOs and stores
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// result to a single output FIFO.
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// Reads only if ALL input FIFOs have data.
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// Source code could be easily adapted to apply any operator on input data.
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//
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// See also fifo_combiner.sv
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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fifo_operator #(
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.WIDTH( 2 ),
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.FWFT_MODE( "TRUE" ),
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.DATA_W( 32 )
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) FO1 (
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.clk( ),
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.nrst( ),
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.r_empty( ),
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.r_req( ),
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.r_data( ),
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.w_full( ), // connect to "almost_full" if FWFT_MODE="FALSE"
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.w_req( ),
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.w_data( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module fifo_operator #( parameter
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WIDTH = 2, // number of input fifo ports to opeate on
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WIDTH_W = clogb2(WIDTH), // input port index width
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FWFT_MODE = "TRUE", // "TRUE" - first word fall-trrough" mode
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// "FALSE" - normal fifo mode
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DATA_W = 32 // data field width
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)(
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input clk, // clock
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input nrst, // inverted reset
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// input ports
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input [WIDTH-1:0] r_empty,
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output [WIDTH-1:0] r_req,
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input [WIDTH-1:0][DATA_W-1:0] r_data,
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// output port
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input w_full,
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output logic w_req,
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output logic [DATA_W-1:0] w_data
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);
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logic r_valid;
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assign r_valid = ~|r_empty && ~w_full;
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assign r_req[WIDTH-1:0] = {WIDTH{r_valid}};
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// buffering read data
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logic r_valid_d1 = 1'b0;
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logic [WIDTH-1:0][DATA_W-1:0] r_data_d1 = '0;
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always_ff @(posedge clk) begin
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if ( ~nrst ) begin
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r_valid_d1 <= 1'b0;
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r_data_d1[WIDTH-1:0] <= '0;
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end else begin
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r_valid_d1 <= r_valid;
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r_data_d1[WIDTH-1:0] <= r_data[WIDTH-1:0];
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end
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end
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// routing data to write port
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generate
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if( FWFT_MODE == "TRUE" ) begin
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always_comb begin
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if ( ~nrst ) begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end else begin
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if( r_valid ) begin
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w_req = 1'b1;
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w_data[DATA_W-1:0] = operator(r_data);
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end else begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end
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end
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end
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end else if( FWFT_MODE == "FALSE" ) begin
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always_comb begin
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if ( ~nrst ) begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end else begin
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if( r_valid_d1 ) begin
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w_req = 1'b1;
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w_data[DATA_W-1:0] = operator(r_data_d1);
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end else begin
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w_req = 1'b0;
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w_data[DATA_W-1:0] = '0;
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end
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end
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end
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end // FWFT_MODE
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endgenerate
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// bitwize OR operator, as an example
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function [DATA_W-1:0] operator (
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input [WIDTH-1:0][DATA_W-1:0] data
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);
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integer i;
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operator[DATA_W-1:0] = '0;
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for( i=0; i<WIDTH; i=i+1 ) begin
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operator[DATA_W-1:0] = operator[DATA_W-1:0] | data[i];
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end
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endfunction
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`include "clogb2.svh"
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endmodule
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‎priority_enc.sv

+29-26
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ priority_enc #(
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module priority_enc #( parameter
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WIDTH = 32,
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WIDTH_W = $clog2(WIDTH)
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WIDTH_W = $clogb2(WIDTH)
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)(
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input [WIDTH-1:0] id, // input data bus
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@@ -36,34 +36,37 @@ module priority_enc #( parameter
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);
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// reversed id[] data
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// conventional operation of priority encoder is when MSB bits have a priority
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logic [WIDTH-1:0] id_r;
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reverse_vector #(
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.WIDTH( WIDTH ) // WIDTH must be >=2
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) reverse_b (
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.in( id[WIDTH-1:0] ),
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.out( id_r[WIDTH-1:0] )
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);
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// reversed id[] data
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// conventional operation of priority encoder is when MSB bits have a priority
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logic [WIDTH-1:0] id_r;
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reverse_vector #(
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.WIDTH( WIDTH ) // WIDTH must be >=2
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) reverse_b (
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.in( id[WIDTH-1:0] ),
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.out( id_r[WIDTH-1:0] )
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);
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leave_one_hot #(
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.WIDTH( WIDTH )
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) one_hot_b (
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.in( id_r[WIDTH-1:0] ),
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.out( od_filt[WIDTH-1:0] )
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);
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leave_one_hot #(
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.WIDTH( WIDTH )
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) one_hot_b (
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.in( id_r[WIDTH-1:0] ),
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.out( od_filt[WIDTH-1:0] )
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);
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logic err_no_hot;
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assign od_valid = ~err_no_hot;
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logic err_no_hot;
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assign od_valid = ~err_no_hot;
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pos2bin #(
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.BIN_WIDTH( WIDTH_W )
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) pos2bin_b (
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.pos( od_filt[WIDTH-1:0] ),
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.bin( od_bin[WIDTH_W-1:0] ),
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pos2bin #(
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.BIN_WIDTH( WIDTH_W )
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) pos2bin_b (
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.pos( od_filt[WIDTH-1:0] ),
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.bin( od_bin[WIDTH_W-1:0] ),
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.err_no_hot( err_no_hot ),
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.err_multi_hot( )
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);
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.err_no_hot( err_no_hot ),
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.err_multi_hot( )
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);
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`include "clogb2.svh"
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endmodule
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