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Commit b4b191c

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Minor code style update
1 parent cf3b4f5 commit b4b191c

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2 files changed

+5
-5
lines changed

2 files changed

+5
-5
lines changed

uart_tx_rx_shifter_tb.sv

+2-2
Original file line numberDiff line numberDiff line change
@@ -101,10 +101,10 @@ logic serial_data;
101101
logic start;
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// continious transfer (no automatic data check implemented)
104-
//assign start = 1'b1;
104+
assign start = 1'b1;
105105

106106
// random transfer (features automatic data check)
107-
assign start = ~tx_busy && &RandomNumber1[11:8];
107+
//assign start = ~tx_busy && &RandomNumber1[11:8];
108108

109109
uart_tx_shifter #(
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.START_BITS( `STB ),

uart_tx_shifter.sv

+3-3
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ always_ff @(posedge clk) begin
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if( tx_start ) begin
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// buffering input data
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tx_data_buf[DATA_BITS-1:0] <= tx_data[DATA_BITS-1:0];
80-
state_cntr[7:0] <= START_BITS-1;
80+
state_cntr[7:0] <= START_BITS - 1'b1;
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tx_state <= tx_state.next();
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end // tx_start
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end // state_cntr
@@ -91,7 +91,7 @@ always_ff @(posedge clk) begin
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state_cntr[7:0]--;
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end else begin
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// transition
94-
state_cntr[7:0] <= DATA_BITS-1;
94+
state_cntr[7:0] <= DATA_BITS - 1'b1;
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tx_state <= tx_state.next();
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end // state_cntr
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@@ -105,7 +105,7 @@ always_ff @(posedge clk) begin
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state_cntr[7:0]--;
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end else begin
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// transition
108-
state_cntr[7:0] <= STOP_BITS-1;
108+
state_cntr[7:0] <= STOP_BITS - 1'b1;
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tx_state <= tx_state.next();
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end // state_cntr
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