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+ // ------------------------------------------------------------------------------
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+ // clogb2.svh
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+ // published as part of https://github.com/pConst/basic_verilog
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+ // Konstantin Pavlov, [email protected]
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+ // ------------------------------------------------------------------------------
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+
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+ // INFO ------------------------------------------------------------------------
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+ // Calculates counter/address width based on specified vector/RAM depth
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+ //
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+ // Function should be instantiated inside a module
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+ // But you are free to call it from anywhere by its hierarchical name
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+ //
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+ // To add clogb2 function to your module:
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+ // `include "clogb2.svh"
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+ //
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+
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+ function integer clogb2 ;
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+ input integer depth;
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+
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+ for ( clogb2= 0 ; depth> 0 ; clogb2= clogb2+ 1 ) begin
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+ depth = depth >> 1 ;
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+ end
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+ endfunction
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