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Added benchmark project for Gowin FPGAs
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‎example_projects/gowin_benchmark/gowin_benchmark.gprj

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<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE gowin-fpga-project>
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<Project>
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<Template>FPGA</Template>
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<Version>5</Version>
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<Device name="GW2A-55C" pn="GW2A-LV55PG1156C7/I6">gw2a55c-009</Device>
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<FileList>
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<File path="src/dynamic_delay.sv" type="file.verilog" enable="1"/>
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<File path="src/main.sv" type="file.verilog" enable="1"/>
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<File path="src/timing.sdc" type="file.sdc" enable="1"/>
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</FileList>
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</Project>

‎example_projects/gowin_benchmark/gowin_benchmark.gprj.user

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<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE ProjectUserData>
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<UserConfig>
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<Version>1.0</Version>
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<FlowState>
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<Process ID="Synthesis" State="2"/>
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<Process ID="Pnr" State="2"/>
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<Process ID="Gao" State="2"/>
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<Process ID="Rtl_Gao" State="2"/>
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</FlowState>
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<ResultFileList>
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<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/gowin_benchmark.vg"/>
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<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/gowin_benchmark.fs"/>
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<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/gowin_benchmark.pin.html"/>
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<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/gowin_benchmark.power.html"/>
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<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/gowin_benchmark.rpt.html"/>
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<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/gowin_benchmark.tr.html"/>
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<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/gowin_benchmark_syn.rpt.html"/>
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<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/gowin_benchmark_syn_rsc.xml"/>
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</ResultFileList>
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<Ui>000000ff00000001fd00000002000000000000010000000282fc0200000001fc00000035000002820000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000140fc0100000001fc00000000000007800000000000fffffffaffffffff0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff00000000000000000000067c0000028200000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000</Ui>
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</UserConfig>

‎example_projects/gowin_benchmark/impl/project_process_config.json

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{
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"Allow_Duplicate_Modules" : false,
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"Annotated_Properties_for_Analyst" : true,
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"BACKGROUND_PROGRAMMING" : false,
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"COMPRESS" : false,
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"CRC_CHECK" : true,
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"Clock_Conversion" : true,
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"DONE" : false,
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"DOWNLOAD_SPEED" : "default",
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"Default_Enum_Encoding" : "default",
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"Disable_Insert_Pad" : false,
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"ENCRYPTION_KEY" : false,
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"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
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"FORMAT" : "binary",
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"FSM Compiler" : true,
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"Fanout_Guide" : 10000,
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"Frequency" : "Auto",
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"Generate_Constraint_File_of_Ports" : false,
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"Generate_IBIS_File" : false,
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"Generate_Plain_Text_Timing_Report" : false,
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"Generate_Post_PNR_Simulation_Model_File" : false,
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"Generate_Post_Place_File" : false,
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"Generate_SDF_File" : false,
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"GwSyn_Loop_Limit" : 2000,
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"Implicit_Initial_Value_Support" : false,
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"IncludePath" : [
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],
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"Initialize_Primitives" : false,
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"JTAG" : false,
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"MODE_IO" : false,
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"MSPI" : false,
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"Multiple_File_Compilation_Unit" : true,
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"Number_of_Critical_Paths" : "",
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"Number_of_Start/End_Points" : "",
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"OUTPUT_BASE_NAME" : "gowin_benchmark",
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"PRINT_BSRAM_VALUE" : true,
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"Pipelining" : true,
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"Place_Option" : "0",
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"Place_register_to_IOB" : true,
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"Process_Configuration_Verion" : "1.0",
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"Promote_Physical_Constraint_Warning_to_Error" : false,
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"Push_Tristates" : true,
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"READY" : false,
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"RECONFIG_N" : false,
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"Ram_RW_Check" : true,
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"Report_Auto-Placed_Io_Information" : false,
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"Resolve_Mixed_Drivers" : false,
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"Resource_Sharing" : true,
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"Retiming" : false,
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"Route_Option" : "0",
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"Run_Timing_Driven" : true,
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"SECURE_MODE" : false,
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"SECURITY_BIT" : true,
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"SPI_FLASH_ADDR" : "00000000",
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"SSPI" : false,
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"Show_All_Warnings" : false,
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"Synthesis On/Off Implemented as Translate On/Off" : false,
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"Synthesize_tool" : "GowinSyn",
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"TopModule" : "main",
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"USERCODE" : "default",
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"Unused_Pin" : "As_input_tri_stated_with_pull_up",
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"Update_Compile_Point_Timing_Data" : false,
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"Use_Clock_Period_for_Unconstrainted IO" : false,
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"Use_SCF" : false,
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"VHDL_Standard" : "VHDL_Std_1993",
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"Verilog_Standard" : "Vlg_Std_Sysv2017",
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"WAKE_UP" : "0",
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"Write_Vendor_Constraint_File" : true,
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"dsp_balance" : false
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}

‎example_projects/gowin_benchmark/readme.txt

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Gowin benchmark project
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=========================
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Konstantin Pavlov, [email protected]
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This project uses dynamic_delay.sv module to model both high-register count and
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combinational-intensive design.
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To see total time spent for the compilation please use some sort of external
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timer. This will give you some quantitive charachteristic of
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your environment processing power.
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You can also compare how different machines and environments deal with this
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typical design when compiling for FPGAs. I use only pure RTL code here with
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intention to leave an opportunity to compare compilation time across all
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possible IDE`s and even across all FPGA vendors.
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"quartus_benchmark" is a similar project for Altera / Intel devices
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"vivado_benchmark" is a similar project for Xilinx / AMD devices
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‎example_projects/gowin_benchmark/src/dynamic_delay.sv

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//--------------------------------------------------------------------------------
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// dynamic_delay.v
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// Konstantin Pavlov, [email protected]
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//--------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Dynamic delay for arbitrary signal
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//
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// CAUTION: The module intentionally does NOT implement error handling when
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// LENGTH is not a multiple of 2. Please handle "out of range"
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// checks externally.
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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dynamic_delay #(
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.LENGTH( 8 )
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//.SEL_W( 3 )
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) DD1 (
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.clk( clk ),
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.nrst( 1'b1 ),
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.ena( 1'b1 ),
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.in( ),
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.sel( ),
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.out( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module dynamic_delay #( parameter
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LENGTH = 8, // maximum delay chain width
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SEL_W = $clog2(LENGTH) // output selector width
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)(
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input clk,
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input nrst,
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input ena,
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input in,
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input [SEL_W-1:0] sel, // output selector
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output logic out
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);
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logic [(LENGTH-1):0] data = 0;
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integer i;
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always_ff @(posedge clk) begin
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if (~nrst) begin
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data[(LENGTH-1):0] <= 0;
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out <= 0;
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end else if (ena) begin
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data[0] <= in;
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for (i=1; i<LENGTH; i=i+1) begin
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data[i] <= data[i-1];
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end
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out <= data[sel[SEL_W-1:0]];
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end
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end
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endmodule

‎example_projects/gowin_benchmark/src/main.sv

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//------------------------------------------------------------------------------
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// main.sv
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// Konstantin Pavlov, [email protected]
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Vivado benchmark project
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//
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// This project uses dynamic_delay.sv module to model both high-register count and
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// combinational-intensive design. See "Messages" tab for TOTAL time
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// spent for compilation. This will give you some quantitive charachteristic
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// of your environment processing power
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`define WIDTH 16
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`define LENGTH 1024
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`define SEL_W $clog2(`LENGTH)
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module main(
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input clk,
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input nrst,
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input [`WIDTH-1:0] id,
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input [`SEL_W-1:0] sel,
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output [`WIDTH-1:0] od
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);
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dynamic_delay #(
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.LENGTH( `LENGTH ),
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.SEL_W( `SEL_W )
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) dd [`WIDTH-1:0] (
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.clk( {`WIDTH{clk}} ),
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.nrst( {`WIDTH{nrst}} ),
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.ena( {`WIDTH{1'b1}} ),
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.in( id[`WIDTH-1:0] ),
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.sel( {`WIDTH{sel[`SEL_W-1:0]}} ),
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.out( od[`WIDTH-1:0] )
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);
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endmodule

‎example_projects/gowin_benchmark/src/timing.sdc

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#------------------------------------------------------------------------------
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# timing.sdc
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# Konstantin Pavlov, [email protected]
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#------------------------------------------------------------------------------
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create_clock -period 10.000 -name clk [get_ports {clk}]
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