Updated SystemVerilog variants of SR trigger featuring dominant logic state

Author: pConst

reset_set.sv

@@ -0,0 +1,45 @@
+//--------------------------------------------------------------------------------
+// reset_set.sv
+// Konstantin Pavlov, [email protected]
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+//  SR trigger variant
+//  No metastable state. SET dominates here
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+reset_set RS1 (
+  .clk( clk ),
+  .nrst( 1'b1 ),
+  .s(  ),
+  .r(  ),
+  .q(  ),
+  .nq(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module reset_set(
+  input wire clk,
+  input wire nrst,
+  input wire s,
+  input wire r,
+  output reg q = 0,   // aka "present state"
+  output wire nq
+);
+
+always_ff @(posedge clk) begin
+  if (~nrst) begin
+    q = 0;
+  end else begin
+    if r q = 0;
+    if s q = 1;
+  end
+end
+
+assign nq = ~q;
+
+endmodule

set_reset.sv

@@ -0,0 +1,45 @@
+//--------------------------------------------------------------------------------
+// set_reset.sv
+// Konstantin Pavlov, [email protected]
+//--------------------------------------------------------------------------------
+
+// INFO --------------------------------------------------------------------------------
+//  SR trigger variant
+//  No metastable state. RESET dominates here
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+set_reset SR1 (
+  .clk( clk ),
+  .nrst( 1'b1 ),
+  .s(  ),
+  .r(  ),
+  .q(  ),
+  .nq(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module set_reset(
+  input wire clk,
+  input wire nrst,
+  input wire s,
+  input wire r,
+  output reg q = 0,   // aka "present state"
+  output wire nq
+);
+
+always_ff @(posedge clk) begin
+  if (~nrst) begin
+    q = 0;
+  end else begin
+    if s q = 1;
+    if r q = 0;
+  end
+end
+
+assign nq = ~q;
+
+endmodule