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// ------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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- // Calculates counter/address width based on specified vector/RAM depth
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- //
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+ // Calculates counter width based on specified vector/RAM depth
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// see also: http://www.sunburst-design.com/papers/CummingsHDLCON2001_Verilog2001.pdf
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//
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+ // WARNING:
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+ // ========
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+ // - clogb2() usage is a quite obsolete technique, left from Verilog-2001 era
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+ // when system function $clog2() was not supported or was implemented falcely
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+ //
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+ // - don`t use clogb2() for new designs! Instead:
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+ //
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+ // - use $clog2(DEPTH) when declaring wr_addr[] pointer, which can refer any
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+ // RAM element from 0 to DEPTH-1
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+ //
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+ // - use $clog2(DEPTH+1) to declare counters, which should hold any walue from
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+ // 0 up to the DEPTH (inclusive)
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+ //
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+ //
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// Compared with system function $clog2():
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// =======================================
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// $clog2(0) = 0; clogb2(0) = 0;
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