|
| 1 | +//------------------------------------------------------------------------------ |
| 2 | +// round_robin_enc.sv |
| 3 | +// Konstantin Pavlov, [email protected] |
| 4 | +//------------------------------------------------------------------------------ |
| 5 | + |
| 6 | +// INFO ------------------------------------------------------------------------- |
| 7 | +// Round robin combinational encoder to select only one bit from the input bus. |
| 8 | +// In contrast to priority encoder, it features cyclically changing priority |
| 9 | +// pointer inside, so every input bit (on aaverage) has equal chance |
| 10 | +// to get to the output |
| 11 | +// |
| 12 | +// This module is meant to be as simple as possible. It is possible to make |
| 13 | +// more efficient, but complicated circuit |
| 14 | +// |
| 15 | +// See also priority_enc.sv |
| 16 | +// See also round_robin_performance_enc.sv |
| 17 | +// |
| 18 | + |
| 19 | + |
| 20 | +/* --- INSTANTIATION TEMPLATE BEGIN --- |
| 21 | +
|
| 22 | +round_robin_enc #( |
| 23 | + .WIDTH( 32 ) |
| 24 | +) RE1 ( |
| 25 | + .clk( clk ), |
| 26 | + .nrst( nrst ), |
| 27 | + .id( ), |
| 28 | + .od_valid( ), |
| 29 | + .od_filt( ), |
| 30 | + .od_bin( ) |
| 31 | +); |
| 32 | +
|
| 33 | +--- INSTANTIATION TEMPLATE END ---*/ |
| 34 | + |
| 35 | + |
| 36 | +module round_robin_enc #( parameter |
| 37 | + WIDTH = 32, |
| 38 | + WIDTH_W = $clog2(WIDTH) |
| 39 | +)( |
| 40 | + input clk, // clock |
| 41 | + input nrst, // inversed reset, synchronous |
| 42 | + |
| 43 | + input [WIDTH-1:0] id, // input data bus |
| 44 | + output logic od_valid, // output valid (some bits are active) |
| 45 | + output logic [WIDTH-1:0] od_filt, // filtered data (only one priority bit active) |
| 46 | + output logic [WIDTH_W-1:0] od_bin // priority bit binary index |
| 47 | +); |
| 48 | + |
| 49 | + |
| 50 | +// current bit selector |
| 51 | +logic [WIDTH_W-1:0] priority_bit = '0; |
| 52 | +always_ff @(posedge clk) begin |
| 53 | + if( ~nrst ) begin |
| 54 | + priority_bit[WIDTH_W-1:0] <= '0; |
| 55 | + end else begin |
| 56 | + if( priority_bit[WIDTH_W-1:0] == WIDTH-1 ) begin |
| 57 | + priority_bit[WIDTH_W-1:0] <= '0; |
| 58 | + end else begin |
| 59 | + priority_bit[WIDTH_W-1:0] <= priority_bit[WIDTH_W-1:0] + 1'b1; |
| 60 | + end // if |
| 61 | + end // if nrst |
| 62 | +end |
| 63 | + |
| 64 | +always_comb begin |
| 65 | + if( id[priority_bit[WIDTH_W-1:0]] ) begin |
| 66 | + od_valid = id[priority_bit[WIDTH_W-1:0]]; |
| 67 | + od_filt[WIDTH-1:0] = 1'b1 << priority_bit[WIDTH_W-1:0]; |
| 68 | + od_bin[WIDTH_W-1:0] = priority_bit[WIDTH_W-1:0]; |
| 69 | + end else begin |
| 70 | + od_valid = 1'b0; |
| 71 | + od_filt[WIDTH-1:0] = '0; |
| 72 | + od_bin[WIDTH_W-1:0] = '0; |
| 73 | + end |
| 74 | +end |
| 75 | + |
| 76 | +endmodule |
0 commit comments