Updated EdgeDetect module instantiation

Author: pConst

main_tb.v renamed to 00_obsolete/main_tb.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// SimWrapper.v
+// ActionBurst2_tb.v
 // Konstantin Pavlov, [email protected]
 //--------------------------------------------------------------------------------
 
@@ -9,7 +9,7 @@
 
 `timescale 1ns / 1ps
 
-module SimWrapper();
+module ActionBurst2_tb();
 
 reg clk200;
 initial begin

ActionBurst2_tb.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// SimWrapper.v
+// ActionBurst_tb.v
 // Konstantin Pavlov, [email protected]
 //--------------------------------------------------------------------------------
 
@@ -9,7 +9,7 @@
 
 `timescale 1ns / 1ps
 
-module SimWrapper();
+module ActionBurst_tb();
 
 reg clk200;
 initial begin

ActionBurst_tb.v

@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Main_TB.v
+// DeBounce_tb.v
 // Konstantin Pavlov, [email protected]
 //--------------------------------------------------------------------------------
 
@@ -9,7 +9,7 @@
 
 `timescale 1ns / 1ps
 
-module Main_tb();
+module DeBounce_tb();
 
 reg clk200;
 initial begin

DeBounce_tb.v

@@ -1,6 +1,5 @@
 //--------------------------------------------------------------------------------
-// Encoder_test project, 201601
-// Main_tb.v
+// Encoder_tb.v
 // Konstantin Pavlov, [email protected]
 //--------------------------------------------------------------------------------
 
@@ -10,7 +9,7 @@
 
 `timescale 1ns / 1ps
 
-module Main_tb();
+module Encoder_tb();
 
 reg clk200;
 initial begin

Encoder_tb.v

@@ -1,6 +1,5 @@
 //--------------------------------------------------------------------------------
-// PulseGen_test project, 201512
-// Main_tb.v
+// PulseGen.v
 // Konstantin Pavlov, [email protected]
 //--------------------------------------------------------------------------------
 
@@ -10,12 +9,12 @@
 
 `timescale 1ns / 1ps
 
-module Main_tb();
+module PulseGen_tb();
 
 reg clk200;
 initial begin
         #0 clk200 = 1;
-        forever 
+        forever
             #2.5 clk200 = ~clk200;
 end
 
@@ -62,6 +61,5 @@ PulseGen PG1 (clk200,~rst,1,1,1'b1,start,busy1,out1);
 
 wire busy2,out2;
 PulseGen PG2 (clk200,~rst,{28'b0,RandomNumber1[3:0]},{28'b0,RandomNumber1[7:4]},1'b0,&RandomNumber1[2:0],busy2,out2);
-    
+
 endmodule
-	

PulseGen_tb.v

@@ -55,11 +55,9 @@ ClkDivider #(
 );
 
 logic [31:0] E_DerivedClocks;
-EdgeDetect #(
-  .WIDTH( 32 )
-) ED1 (
-  .clk( clk200 ),
-  .nrst( nrst_once ),
+EdgeDetect ED1[31:0] (
+  .clk( {32{clk200}} ),
+  .nrst( {32{nrst_once}} ),
   .in( DerivedClocks[31:0] ),
   .rising( E_DerivedClocks[31:0] ),
   .falling(  ),

ReverseVector_tb.sv

@@ -55,11 +55,9 @@ ClkDivider #(
 );
 
 logic [31:0] E_DerivedClocks;
-EdgeDetect #(
-  .WIDTH( 32 )
-) ED1 (
-  .clk( clk200 ),
-  .nrst( nrst_once ),
+EdgeDetect ED1[31:0] (
+  .clk( {32{clk200}} ),
+  .nrst( {32{nrst_once}} ),
   .in( DerivedClocks[31:0] ),
   .rising( E_DerivedClocks[31:0] ),
   .falling(  ),

bin2pos_tb.sv

@@ -55,11 +55,9 @@ ClkDivider #(
 );
 
 logic [31:0] E_DerivedClocks;
-EdgeDetect #(
-  .WIDTH( 32 )
-) ED1 (
-  .clk( clk200 ),
-  .nrst( nrst_once ),
+EdgeDetect ED1[31:0] (
+  .clk( {32{clk200}} ),
+  .nrst( {32{nrst_once}} ),
   .in( DerivedClocks[31:0] ),
   .rising( E_DerivedClocks[31:0] ),
   .falling(  ),

fifo_tb.sv

@@ -55,11 +55,9 @@ ClkDivider #(
 );
 
 logic [31:0] E_DerivedClocks;
-EdgeDetect #(
-  .WIDTH( 32 )
-) ED1 (
-  .clk( clk200 ),
-  .nrst( nrst_once ),
+EdgeDetect ED1[31:0] (
+  .clk( {32{clk200}} ),
+  .nrst( {32{nrst_once}} ),
   .in( DerivedClocks[31:0] ),
   .rising( E_DerivedClocks[31:0] ),
   .falling(  ),

lifo_tb.sv

@@ -54,11 +54,9 @@ ClkDivider #(
 );
 
 logic [31:0] E_DerivedClocks;
-EdgeDetect #(
-  .WIDTH( 32 )
-) ED1 (
-  .clk( clk200 ),
-  .nrst( nrst_once ),
+EdgeDetect ED1[31:0] (
+  .clk( {32{clk200}} ),
+  .nrst( {32{nrst_once}} ),
   .in( DerivedClocks[31:0] ),
   .rising( E_DerivedClocks[31:0] ),
   .falling(  ),

main_tb.sv

@@ -55,11 +55,9 @@ ClkDivider #(
 );
 
 logic [31:0] E_DerivedClocks;
-EdgeDetect #(
-  .WIDTH( 32 )
-) ED1 (
-  .clk( clk200 ),
-  .nrst( nrst_once ),
+EdgeDetect ED1[31:0] (
+  .clk( {32{clk200}} ),
+  .nrst( {32{nrst_once}} ),
   .in( DerivedClocks[31:0] ),
   .rising( E_DerivedClocks[31:0] ),
   .falling(  ),