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Updated benchmark projects. Added 'benchmark_results.txt' that i got on my machine
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‎example_projects/benchmark_results.txt

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@@ -0,0 +1,18 @@
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Compilation time results for reference benchmark projects
4+
=========================================================
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6+
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Xeon E5-2630 v4, RAM 32GB, Windows 7
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------------------------------------
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quartus_benchmark - 4m 58s ( Quartus Lite 17 )
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vivado_benchmark - 5m 58s ( Vivado 2019.2 )
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gowin_benchmark - 4m 15s ( Gowin_V1.9.6Beta )
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ise_benchmark - 9m 10s ( ISE 12.4 )
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Xeon E5-2630 v4, RAM 32GB, Windows 7, project files on RamDisk
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--------------------------------------------------------------
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quartus_benchmark - 4m 57s
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vivado_benchmark - 5m 56s

‎example_projects/gowin_benchmark/src/dynamic_delay.sv

+51-24
Original file line numberDiff line numberDiff line change
@@ -4,55 +4,82 @@
44
//--------------------------------------------------------------------------------
55

66
// INFO --------------------------------------------------------------------------------
7-
// Dynamic delay for arbitrary signal
7+
// Dynamic delay for arbitrary signal.
88
//
9-
// CAUTION: The module intentionally does NOT implement error handling when
10-
// LENGTH is not a multiple of 2. Please handle "out of range"
11-
// checks externally.
9+
// Incoming data elements have WIDTH bits each. Module does serialization of
10+
// input data and outputs flattened bits, based on provided selector value.
11+
// You can perform delays bit-wize, not just element-wize.
12+
//
13+
// CAUTION: Be careful selecting last, most-delayed "WIDTH" number of bits.
14+
// The module intentionally does NOT implement "out of range"
15+
// checks. Please handle them externally.
16+
1217

1318

1419
/* --- INSTANTIATION TEMPLATE BEGIN ---
1520
1621
dynamic_delay #(
17-
.LENGTH( 8 )
18-
//.SEL_W( 3 )
19-
) DD1 (
22+
.LENGTH( 3 ),
23+
.WIDTH( 4 )
24+
) M (
2025
.clk( clk ),
21-
.nrst( 1'b1 ),
26+
.nrst( nrst ),
2227
.ena( 1'b1 ),
23-
.in( ),
24-
.sel( ),
25-
.out( )
28+
.in( in_data[3:0] ),
29+
.sel( sel[3:0] ),
30+
.out( out_data[3:0] )
2631
);
2732
2833
--- INSTANTIATION TEMPLATE END ---*/
2934

3035

3136
module dynamic_delay #( parameter
32-
LENGTH = 8, // maximum delay chain width
33-
SEL_W = $clog2(LENGTH) // output selector width
37+
LENGTH = 63, // maximum delay chain length
38+
WIDTH = 4, // data width
39+
40+
SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
41+
// plus one is for zero delay element
3442
)(
3543
input clk,
3644
input nrst,
3745
input ena,
38-
input in,
39-
input [SEL_W-1:0] sel, // output selector
40-
output logic out
46+
input [WIDTH-1:0] in, // input data
47+
// bit in[0] is the "oldest" one
48+
// bit in[WIDTH] is considered the most recent
49+
input [SEL_W-1:0] sel, // output selector
50+
output logic [WIDTH-1:0] out // output data
4151
);
4252

43-
logic [(LENGTH-1):0] data = 0;
53+
54+
55+
logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;
56+
57+
// packed vector includes extra bits
58+
logic [(LENGTH+1)*WIDTH-1:0] pack_data;
59+
assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;
4460

4561
integer i;
4662
always_ff @(posedge clk) begin
47-
if (~nrst) begin
48-
data[(LENGTH-1):0] <= 0;
49-
out <= 0;
63+
if( ~nrst ) begin
64+
// reset all data except zero element
65+
for( i=1; i<(LENGTH+1); i=i+1 ) begin
66+
data[i][WIDTH-1:0] <= '0;
67+
end
5068
end else if (ena) begin
51-
data[0] <= in;
52-
for (i=1; i<LENGTH; i=i+1) begin
53-
data[i] <= data[i-1];
69+
for( i=1; i<(LENGTH+1); i=i+1 ) begin
70+
data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
5471
end
55-
out <= data[sel[SEL_W-1:0]];
72+
end
73+
end
74+
75+
integer j;
76+
always_comb begin
77+
// zero element assignment
78+
data[0][WIDTH-1:0] <= in[WIDTH-1:0];
79+
80+
// output selector, sel==0 gives non-delayed output
81+
for( j=0; j<WIDTH; j=j+1 ) begin
82+
out[j] <= pack_data[sel[SEL_W-1:0]+j];
5683
end
5784
end
5885

‎example_projects/gowin_benchmark/src/main.sv

+1
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ module main(
2828

2929
dynamic_delay #(
3030
.LENGTH( `LENGTH ),
31+
.WIDTH( 1 ),
3132
.SEL_W( `SEL_W )
3233
) dd [`WIDTH-1:0] (
3334
.clk( {`WIDTH{clk}} ),

‎example_projects/quartus_benchmark/dynamic_delay.sv

+51-24
Original file line numberDiff line numberDiff line change
@@ -4,55 +4,82 @@
44
//--------------------------------------------------------------------------------
55

66
// INFO --------------------------------------------------------------------------------
7-
// Dynamic delay for arbitrary signal
7+
// Dynamic delay for arbitrary signal.
88
//
9-
// CAUTION: The module intentionally does NOT implement error handling when
10-
// LENGTH is not a multiple of 2. Please handle "out of range"
11-
// checks externally.
9+
// Incoming data elements have WIDTH bits each. Module does serialization of
10+
// input data and outputs flattened bits, based on provided selector value.
11+
// You can perform delays bit-wize, not just element-wize.
12+
//
13+
// CAUTION: Be careful selecting last, most-delayed "WIDTH" number of bits.
14+
// The module intentionally does NOT implement "out of range"
15+
// checks. Please handle them externally.
16+
1217

1318

1419
/* --- INSTANTIATION TEMPLATE BEGIN ---
1520
1621
dynamic_delay #(
17-
.LENGTH( 8 )
18-
//.SEL_W( 3 )
19-
) DD1 (
22+
.LENGTH( 3 ),
23+
.WIDTH( 4 )
24+
) M (
2025
.clk( clk ),
21-
.nrst( 1'b1 ),
26+
.nrst( nrst ),
2227
.ena( 1'b1 ),
23-
.in( ),
24-
.sel( ),
25-
.out( )
28+
.in( in_data[3:0] ),
29+
.sel( sel[3:0] ),
30+
.out( out_data[3:0] )
2631
);
2732
2833
--- INSTANTIATION TEMPLATE END ---*/
2934

3035

3136
module dynamic_delay #( parameter
32-
LENGTH = 8, // maximum delay chain width
33-
SEL_W = $clog2(LENGTH) // output selector width
37+
LENGTH = 63, // maximum delay chain length
38+
WIDTH = 4, // data width
39+
40+
SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
41+
// plus one is for zero delay element
3442
)(
3543
input clk,
3644
input nrst,
3745
input ena,
38-
input in,
39-
input [SEL_W-1:0] sel, // output selector
40-
output logic out
46+
input [WIDTH-1:0] in, // input data
47+
// bit in[0] is the "oldest" one
48+
// bit in[WIDTH] is considered the most recent
49+
input [SEL_W-1:0] sel, // output selector
50+
output logic [WIDTH-1:0] out // output data
4151
);
4252

43-
logic [(LENGTH-1):0] data = 0;
53+
54+
55+
logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;
56+
57+
// packed vector includes extra bits
58+
logic [(LENGTH+1)*WIDTH-1:0] pack_data;
59+
assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;
4460

4561
integer i;
4662
always_ff @(posedge clk) begin
47-
if (~nrst) begin
48-
data[(LENGTH-1):0] <= 0;
49-
out <= 0;
63+
if( ~nrst ) begin
64+
// reset all data except zero element
65+
for( i=1; i<(LENGTH+1); i=i+1 ) begin
66+
data[i][WIDTH-1:0] <= '0;
67+
end
5068
end else if (ena) begin
51-
data[0] <= in;
52-
for (i=1; i<LENGTH; i=i+1) begin
53-
data[i] <= data[i-1];
69+
for( i=1; i<(LENGTH+1); i=i+1 ) begin
70+
data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
5471
end
55-
out <= data[sel[SEL_W-1:0]];
72+
end
73+
end
74+
75+
integer j;
76+
always_comb begin
77+
// zero element assignment
78+
data[0][WIDTH-1:0] <= in[WIDTH-1:0];
79+
80+
// output selector, sel==0 gives non-delayed output
81+
for( j=0; j<WIDTH; j=j+1 ) begin
82+
out[j] <= pack_data[sel[SEL_W-1:0]+j];
5683
end
5784
end
5885

‎example_projects/quartus_benchmark/main.sv

+1
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ module main(
2828

2929
dynamic_delay #(
3030
.LENGTH( `LENGTH ),
31+
.WIDTH( 1 ),
3132
.SEL_W( `SEL_W )
3233
) dd [`WIDTH-1:0] (
3334
.clk( {`WIDTH{clk}} ),

‎example_projects/vivado_benchmark/vivado_benchmark.srcs/sources_1/dynamic_delay.sv

+51-24
Original file line numberDiff line numberDiff line change
@@ -4,55 +4,82 @@
44
//--------------------------------------------------------------------------------
55

66
// INFO --------------------------------------------------------------------------------
7-
// Dynamic delay for arbitrary signal
7+
// Dynamic delay for arbitrary signal.
88
//
9-
// CAUTION: The module intentionally does NOT implement error handling when
10-
// LENGTH is not a multiple of 2. Please handle "out of range"
11-
// checks externally.
9+
// Incoming data elements have WIDTH bits each. Module does serialization of
10+
// input data and outputs flattened bits, based on provided selector value.
11+
// You can perform delays bit-wize, not just element-wize.
12+
//
13+
// CAUTION: Be careful selecting last, most-delayed "WIDTH" number of bits.
14+
// The module intentionally does NOT implement "out of range"
15+
// checks. Please handle them externally.
16+
1217

1318

1419
/* --- INSTANTIATION TEMPLATE BEGIN ---
1520
1621
dynamic_delay #(
17-
.LENGTH( 8 )
18-
//.SEL_W( 3 )
19-
) DD1 (
22+
.LENGTH( 3 ),
23+
.WIDTH( 4 )
24+
) M (
2025
.clk( clk ),
21-
.nrst( 1'b1 ),
26+
.nrst( nrst ),
2227
.ena( 1'b1 ),
23-
.in( ),
24-
.sel( ),
25-
.out( )
28+
.in( in_data[3:0] ),
29+
.sel( sel[3:0] ),
30+
.out( out_data[3:0] )
2631
);
2732
2833
--- INSTANTIATION TEMPLATE END ---*/
2934

3035

3136
module dynamic_delay #( parameter
32-
LENGTH = 8, // maximum delay chain width
33-
SEL_W = $clog2(LENGTH) // output selector width
37+
LENGTH = 63, // maximum delay chain length
38+
WIDTH = 4, // data width
39+
40+
SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
41+
// plus one is for zero delay element
3442
)(
3543
input clk,
3644
input nrst,
3745
input ena,
38-
input in,
39-
input [SEL_W-1:0] sel, // output selector
40-
output logic out
46+
input [WIDTH-1:0] in, // input data
47+
// bit in[0] is the "oldest" one
48+
// bit in[WIDTH] is considered the most recent
49+
input [SEL_W-1:0] sel, // output selector
50+
output logic [WIDTH-1:0] out // output data
4151
);
4252

43-
logic [(LENGTH-1):0] data = 0;
53+
54+
55+
logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;
56+
57+
// packed vector includes extra bits
58+
logic [(LENGTH+1)*WIDTH-1:0] pack_data;
59+
assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;
4460

4561
integer i;
4662
always_ff @(posedge clk) begin
47-
if (~nrst) begin
48-
data[(LENGTH-1):0] <= 0;
49-
out <= 0;
63+
if( ~nrst ) begin
64+
// reset all data except zero element
65+
for( i=1; i<(LENGTH+1); i=i+1 ) begin
66+
data[i][WIDTH-1:0] <= '0;
67+
end
5068
end else if (ena) begin
51-
data[0] <= in;
52-
for (i=1; i<LENGTH; i=i+1) begin
53-
data[i] <= data[i-1];
69+
for( i=1; i<(LENGTH+1); i=i+1 ) begin
70+
data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
5471
end
55-
out <= data[sel[SEL_W-1:0]];
72+
end
73+
end
74+
75+
integer j;
76+
always_comb begin
77+
// zero element assignment
78+
data[0][WIDTH-1:0] <= in[WIDTH-1:0];
79+
80+
// output selector, sel==0 gives non-delayed output
81+
for( j=0; j<WIDTH; j=j+1 ) begin
82+
out[j] <= pack_data[sel[SEL_W-1:0]+j];
5683
end
5784
end
5885

‎example_projects/vivado_benchmark/vivado_benchmark.srcs/sources_1/main.sv

+1
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ module main(
2828

2929
dynamic_delay #(
3030
.LENGTH( `LENGTH ),
31+
.WIDTH( 1 ),
3132
.SEL_W( `SEL_W )
3233
) dd [`WIDTH-1:0] (
3334
.clk( {`WIDTH{clk}} ),

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