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Added hex2ascii as a standalone module
1 parent 45a1621 commit 58c10b0

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2 files changed

+68
-31
lines changed

2 files changed

+68
-31
lines changed

hex2ascii.sv

+37
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
//------------------------------------------------------------------------------
2+
// hex2ascii.sv
3+
// published as part of https://github.com/pConst/basic_verilog
4+
// Konstantin Pavlov, [email protected]
5+
//------------------------------------------------------------------------------
6+
7+
// INFO ------------------------------------------------------------------------
8+
// Converts 4-bit binary nibble to 8-bit human-readable ASCII char
9+
// For example, 4'b1111 befomes an "F" char, 4'b0100 becomes "4" char
10+
//
11+
12+
13+
/* --- INSTANTIATION TEMPLATE BEGIN ---
14+
15+
hex2ascii HA (
16+
.hex( ),
17+
.ascii( )
18+
);
19+
20+
--- INSTANTIATION TEMPLATE END ---*/
21+
22+
23+
module hex2ascii (
24+
input [3:0] hex,
25+
output [7:0] ascii
26+
);
27+
28+
always_comb begin
29+
if( hex[3:0] < 4'hA ) begin
30+
ascii[7:0] = hex[3:0] + 8'd48; // 0 hex -> 48 ascii
31+
end else begin
32+
ascii[7:0] = hex[3:0] + 8'd55; // A hex -> 65 ascii
33+
end
34+
end
35+
36+
endmodule
37+

uart_debug_printer.sv

+31-31
Original file line numberDiff line numberDiff line change
@@ -75,18 +75,18 @@ module uart_debug_printer #( parameter
7575
end else begin
7676
case ( seq_cntr[7:0] )
7777

78-
7'd0: begin
78+
8'd0: begin
7979
if( ~empty && ~tx_busy ) begin
80-
tx_char[7:0] <= (r_rnw)?(7'd82):(7'd87); // "R"/"W" symbol
80+
tx_char[7:0] <= (r_rnw)?(8'd82):(8'd87); // "R"/"W" symbol
8181
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
8282
tx_start <= 1'b1;
8383
end else begin
8484
tx_start <= 1'b0;
8585
end
8686
end
87-
7'd1: begin
87+
8'd1: begin
8888
if( ~tx_start && ~tx_busy ) begin
89-
tx_char[7:0] <= 7'd32; // "_" divider symbol =======================
89+
tx_char[7:0] <= 8'd32; // "_" divider symbol =======================
9090
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
9191
tx_start <= 1'b1;
9292
end else begin
@@ -95,7 +95,7 @@ module uart_debug_printer #( parameter
9595
end
9696

9797

98-
7'd2: begin
98+
8'd2: begin
9999
if( ~tx_start && ~tx_busy ) begin
100100
tx_char[7:0] <= hex2ascii(r_addr[31:28]);
101101
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -104,7 +104,7 @@ module uart_debug_printer #( parameter
104104
tx_start <= 1'b0;
105105
end
106106
end
107-
7'd3: begin
107+
8'd3: begin
108108
if( ~tx_start && ~tx_busy ) begin
109109
tx_char[7:0] <= hex2ascii(r_addr[27:24]);
110110
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -113,7 +113,7 @@ module uart_debug_printer #( parameter
113113
tx_start <= 1'b0;
114114
end
115115
end
116-
7'd4: begin
116+
8'd4: begin
117117
if( ~tx_start && ~tx_busy ) begin
118118
tx_char[7:0] <= hex2ascii(r_addr[23:20]);
119119
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -122,7 +122,7 @@ module uart_debug_printer #( parameter
122122
tx_start <= 1'b0;
123123
end
124124
end
125-
7'd5: begin
125+
8'd5: begin
126126
if( ~tx_start && ~tx_busy ) begin
127127
tx_char[7:0] <= hex2ascii(r_addr[19:16]);
128128
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -131,16 +131,16 @@ module uart_debug_printer #( parameter
131131
tx_start <= 1'b0;
132132
end
133133
end
134-
7'd6: begin
134+
8'd6: begin
135135
if( ~tx_start && ~tx_busy ) begin
136-
tx_char[7:0] <= 7'd95; // "_" symbol
136+
tx_char[7:0] <= 8'd95; // "_" symbol
137137
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
138138
tx_start <= 1'b1;
139139
end else begin
140140
tx_start <= 1'b0;
141141
end
142142
end
143-
7'd7: begin
143+
8'd7: begin
144144
if( ~tx_start && ~tx_busy ) begin
145145
tx_char[7:0] <= hex2ascii(r_addr[15:12]);
146146
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -149,7 +149,7 @@ module uart_debug_printer #( parameter
149149
tx_start <= 1'b0;
150150
end
151151
end
152-
7'd8: begin
152+
8'd8: begin
153153
if( ~tx_start && ~tx_busy ) begin
154154
tx_char[7:0] <= hex2ascii(r_addr[11:8]);
155155
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -158,7 +158,7 @@ module uart_debug_printer #( parameter
158158
tx_start <= 1'b0;
159159
end
160160
end
161-
7'd9: begin
161+
8'd9: begin
162162
if( ~tx_start && ~tx_busy ) begin
163163
tx_char[7:0] <= hex2ascii(r_addr[7:4]);
164164
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -167,7 +167,7 @@ module uart_debug_printer #( parameter
167167
tx_start <= 1'b0;
168168
end
169169
end
170-
7'd10: begin
170+
8'd10: begin
171171
if( ~tx_start && ~tx_busy ) begin
172172
tx_char[7:0] <= hex2ascii(r_addr[3:0]);
173173
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -177,17 +177,17 @@ module uart_debug_printer #( parameter
177177
end
178178
end
179179

180-
7'd11: begin
180+
8'd11: begin
181181
if( ~tx_start && ~tx_busy ) begin
182-
tx_char[7:0] <= 7'd32; // "-" divider symbol =======================
182+
tx_char[7:0] <= 8'd32; // "-" divider symbol =======================
183183
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
184184
tx_start <= 1'b1;
185185
end else begin
186186
tx_start <= 1'b0;
187187
end
188188
end
189189

190-
7'd12: begin
190+
8'd12: begin
191191
if( ~tx_start && ~tx_busy ) begin
192192
tx_char[7:0] <= hex2ascii(r_data[31:28]);
193193
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -196,7 +196,7 @@ module uart_debug_printer #( parameter
196196
tx_start <= 1'b0;
197197
end
198198
end
199-
7'd13: begin
199+
8'd13: begin
200200
if( ~tx_start && ~tx_busy ) begin
201201
tx_char[7:0] <= hex2ascii(r_data[27:24]);
202202
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -205,7 +205,7 @@ module uart_debug_printer #( parameter
205205
tx_start <= 1'b0;
206206
end
207207
end
208-
7'd14: begin
208+
8'd14: begin
209209
if( ~tx_start && ~tx_busy ) begin
210210
tx_char[7:0] <= hex2ascii(r_data[23:20]);
211211
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -214,7 +214,7 @@ module uart_debug_printer #( parameter
214214
tx_start <= 1'b0;
215215
end
216216
end
217-
7'd15: begin
217+
8'd15: begin
218218
if( ~tx_start && ~tx_busy ) begin
219219
tx_char[7:0] <= hex2ascii(r_data[19:16]);
220220
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -223,16 +223,16 @@ module uart_debug_printer #( parameter
223223
tx_start <= 1'b0;
224224
end
225225
end
226-
7'd16: begin
226+
8'd16: begin
227227
if( ~tx_start && ~tx_busy ) begin
228-
tx_char[7:0] <= 7'd95; // "_" symbol
228+
tx_char[7:0] <= 8'd95; // "_" symbol
229229
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
230230
tx_start <= 1'b1;
231231
end else begin
232232
tx_start <= 1'b0;
233233
end
234234
end
235-
7'd17: begin
235+
8'd17: begin
236236
if( ~tx_start && ~tx_busy ) begin
237237
tx_char[7:0] <= hex2ascii(r_data[15:12]);
238238
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -241,7 +241,7 @@ module uart_debug_printer #( parameter
241241
tx_start <= 1'b0;
242242
end
243243
end
244-
7'd18: begin
244+
8'd18: begin
245245
if( ~tx_start && ~tx_busy ) begin
246246
tx_char[7:0] <= hex2ascii(r_data[11:8]);
247247
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -250,7 +250,7 @@ module uart_debug_printer #( parameter
250250
tx_start <= 1'b0;
251251
end
252252
end
253-
7'd19: begin
253+
8'd19: begin
254254
if( ~tx_start && ~tx_busy ) begin
255255
tx_char[7:0] <= hex2ascii(r_data[7:4]);
256256
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -259,7 +259,7 @@ module uart_debug_printer #( parameter
259259
tx_start <= 1'b0;
260260
end
261261
end
262-
7'd20: begin
262+
8'd20: begin
263263
if( ~tx_start && ~tx_busy ) begin
264264
tx_char[7:0] <= hex2ascii(r_data[3:0]);
265265
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
@@ -269,9 +269,9 @@ module uart_debug_printer #( parameter
269269
end
270270
end
271271

272-
7'd21: begin
272+
8'd21: begin
273273
if( ~tx_start && ~tx_busy ) begin
274-
tx_char[7:0] <= 7'd13; // "CR" symbol
274+
tx_char[7:0] <= 8'd13; // "CR" symbol
275275
seq_cntr[7:0] <= seq_cntr[7:0] + 1'b1;
276276
r_req <= 1'b1; // fifo data ack begin
277277
tx_start <= 1'b1;
@@ -280,7 +280,7 @@ module uart_debug_printer #( parameter
280280
end
281281
end
282282

283-
7'd22: begin
283+
8'd22: begin
284284
if( ~tx_busy ) begin
285285
tx_start <= 1'b0;
286286
seq_cntr[7:0] <= '0;
@@ -317,9 +317,9 @@ module uart_debug_printer #( parameter
317317
input [3:0] hex
318318
);
319319
if( hex[3:0] < 4'hA ) begin
320-
hex2ascii[7:0] = hex[3:0] + 7'd48; // 0 hex -> 48 ascii
320+
hex2ascii[7:0] = hex[3:0] + 8'd48; // 0 hex -> 48 ascii
321321
end else begin
322-
hex2ascii[7:0] = hex[3:0] + 7'd55; // A hex -> 65 ascii
322+
hex2ascii[7:0] = hex[3:0] + 8'd55; // A hex -> 65 ascii
323323
end // if
324324
endfunction
325325

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