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HLS template project and scripts update
1 parent 8b1b2ef commit 454f71e

27 files changed

+125
-52
lines changed

‎example_projects/vitis_hls_test_prj_template_v1/hls_operator.cpp

-19
This file was deleted.

‎example_projects/vitis_hls_test_prj_template_v1/hls_operator.h

-9
This file was deleted.

‎example_projects/vitis_hls_test_prj_template_v2/.gitignore

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#------------------------------------------------------------------------------
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# .gitignore for Vitis HLS projects
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# published as part of https://github.com/pConst/basic_verilog
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# Konstantin Pavlov, [email protected]
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#------------------------------------------------------------------------------
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# INFO ------------------------------------------------------------------------
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# rename the file to ".gitignore" and place into your HLS project directory
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#
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/prj
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vitis_hls.log
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‎example_projects/vitis_hls_test_prj_template_v1/run_hls.tcl renamed to ‎example_projects/vitis_hls_test_prj_template_v2/run_hls.tcl

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#------------------------------------------------------------------------------
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66
# Create a project
7-
open_project proj -reset
8-
add_files hls_operator.cpp
9-
add_files -tb hls_operator_tb.cpp
7+
open_project prj -reset
8+
add_files src/hls_operator.cpp
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add_files -tb src/hls_operator_tb.cpp
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set_top hls_operator
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# Create a solution

‎example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.cpp

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//------------------------------------------------------------------------------
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, [email protected]
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//------------------------------------------------------------------------------
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#include "ap_int.h"
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#include "hls_stream.h"
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void hls_operator(
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hls::stream<int> &a,
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hls::stream<int> &b,
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hls::stream<int> &c,
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hls::stream<int> &d
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){
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#pragma HLS DATAFLOW disable_start_propagation
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#pragma HLS INTERFACE mode=ap_ctrl_none port=return
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#pragma HLS INTERFACE port=a ap_fifo
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#pragma HLS INTERFACE port=b axis
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#pragma HLS INTERFACE port=c ap_fifo
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#pragma HLS INTERFACE port=d axis
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c.write( a.read() + b.read() );
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d.write( a.read() - b.read() );
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}
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‎example_projects/vitis_hls_test_prj_template_v2/src/hls_operator.h

Whitespace-only changes.

‎example_projects/vitis_hls_test_prj_template_v1/hls_operator_tb.cpp renamed to ‎example_projects/vitis_hls_test_prj_template_v2/src/hls_operator_tb.cpp

File renamed without changes.

‎example_projects/vitis_hls_test_prj_template_v1/vitis_hls_clean.sh renamed to ‎example_projects/vitis_hls_test_prj_template_v2/vitis_hls_clean.sh

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@@ -7,7 +7,7 @@
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# Script to clean Vitis HLS project
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
99

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rm -rf proj
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rm -rf prj
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rm vitis_hls.log
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‎example_projects/vitis_hls_test_prj_template_v1/vitis_hls_cosim.sh renamed to ‎example_projects/vitis_hls_test_prj_template_v2/vitis_hls_cosim.sh

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# Script to perform HLS component co-simulation
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

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if [ ! -d "./proj" ]; then
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if [ ! -d "./prj" ]; then
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source vitis_hls_csynth.sh
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fi
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‎example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csim.sh renamed to ‎example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csim.sh

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# Script to perform HLS component simulation
99
# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
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if [ ! -d "./prj" ]; then
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source vitis_hls_csynth.sh
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fi
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‎example_projects/vitis_hls_test_prj_template_v2/vitis_hls_csynth.sh

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#! /usr/bin/env bash
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#------------------------------------------------------------------------------
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# published as part of https://github.com/pConst/basic_verilog
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# Konstantin Pavlov, [email protected]
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#------------------------------------------------------------------------------
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# Script to initialize HLS project solution and make CSYNTH compilation step
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
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rm -rf ./prj/sol1/syn
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rm -rf ./prj/sol1/impl
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vitis_hls -f run_hls.tcl
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# open top Verilog
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subl ./prj/sol1/syn/verilog/hls_operator.v
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# open main report
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subl ./prj/sol1/syn/report/csynth.rpt
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‎example_projects/vitis_hls_test_prj_template_v1/vitis_hls_export.sh renamed to ‎example_projects/vitis_hls_test_prj_template_v2/vitis_hls_export.sh

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# Script to export HLS component to Vivado IP catalog
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
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if [ ! -d "./prj" ]; then
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source vitis_hls_csynth.sh
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fi
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‎scripts_for_xilinx_hls/vitis_hls_open_gui.sh renamed to ‎example_projects/vitis_hls_test_prj_template_v2/vitis_hls_gui.sh

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# Script to open Vitis HLS GUI
99
# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
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if [ ! -d "./prj" ]; then
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source vitis_hls_csynth.sh
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fi
1414

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vitis_hls -p proj
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nohup vitis_hls -p prj &> /dev/null & disown
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‎example_projects/vitis_hls_test_prj_template_v1/vitis_hls_impl.sh renamed to ‎example_projects/vitis_hls_test_prj_template_v2/vitis_hls_impl.sh

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# Script to perform HLS IP synthesis and implementation
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
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if [ ! -d "./prj" ]; then
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source vitis_hls_csynth.sh
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fi
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‎example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csynth.sh renamed to ‎example_projects/vitis_hls_test_prj_template_v2/vitis_hls_killall.sh

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#! /usr/bin/env bash
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#------------------------------------------------------------------------------
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# published as part of https://github.com/pConst/basic_verilog
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# Konstantin Pavlov, [email protected]
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#------------------------------------------------------------------------------
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7-
# Script to initialize HLS project solution and make CSYNTH compilation step
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# Script to open Vitis HLS GUI
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
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10-
vitis_hls -f run_hls.tcl
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killall vitis_hls
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‎example_projects/vitis_hls_test_prj_template_v1/vitis_hls_syn.sh renamed to ‎example_projects/vitis_hls_test_prj_template_v2/vitis_hls_syn.sh

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# Script to perform HLS IP synthesis
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
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if [ ! -d "./prj" ]; then
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source vitis_hls_csynth.sh
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fi
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‎gitignores/.gitignore_vitis_hls

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#------------------------------------------------------------------------------
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# .gitignore for Vitis HLS projects
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# published as part of https://github.com/pConst/basic_verilog
4+
# Konstantin Pavlov, [email protected]
5+
#------------------------------------------------------------------------------
6+
7+
# INFO ------------------------------------------------------------------------
8+
# rename the file to ".gitignore" and place into your HLS project directory
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#
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/prj
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vitis_hls.log
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‎scripts_for_xilinx_hls/run_hls.tcl

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#------------------------------------------------------------------------------
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# Create a project
7-
open_project proj -reset
8-
add_files hls_operator.cpp
9-
add_files -tb hls_operator_tb.cpp
7+
open_project prj -reset
8+
add_files src/hls_operator.cpp
9+
add_files -tb src/hls_operator_tb.cpp
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set_top hls_operator
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1212
# Create a solution

‎scripts_for_xilinx_hls/vitis_hls_clean.sh

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@@ -7,7 +7,7 @@
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# Script to clean Vitis HLS project
88
# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
99

10-
rm -rf proj
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rm -rf prj
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rm vitis_hls.log
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‎scripts_for_xilinx_hls/vitis_hls_cosim.sh

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# Script to perform HLS component co-simulation
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
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if [ ! -d "./prj" ]; then
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source vitis_hls_csynth.sh
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fi
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‎scripts_for_xilinx_hls/vitis_hls_csim.sh

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# Script to perform HLS component simulation
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
11+
if [ ! -d "./prj" ]; then
1212
source vitis_hls_csynth.sh
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fi
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‎scripts_for_xilinx_hls/vitis_hls_csynth.sh

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@@ -7,5 +7,16 @@
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# Script to initialize HLS project solution and make CSYNTH compilation step
88
# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
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12+
rm -rf ./prj/sol1/syn
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rm -rf ./prj/sol1/impl
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vitis_hls -f run_hls.tcl
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# open top Verilog
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subl ./prj/sol1/syn/verilog/hls_operator.v
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# open main report
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subl ./prj/sol1/syn/report/csynth.rpt
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‎scripts_for_xilinx_hls/vitis_hls_export.sh

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@@ -8,7 +8,7 @@
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# Script to export HLS component to Vivado IP catalog
99
# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
11+
if [ ! -d "./prj" ]; then
1212
source vitis_hls_csynth.sh
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fi
1414

‎example_projects/vitis_hls_test_prj_template_v1/vitis_hls_open_gui.sh renamed to ‎scripts_for_xilinx_hls/vitis_hls_gui.sh

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@@ -8,9 +8,9 @@
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# Script to open Vitis HLS GUI
99
# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
11+
if [ ! -d "./prj" ]; then
1212
source vitis_hls_csynth.sh
1313
fi
1414

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vitis_hls -p proj
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nohup vitis_hls -p prj &> /dev/null & disown
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‎scripts_for_xilinx_hls/vitis_hls_impl.sh

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@@ -8,7 +8,7 @@
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# Script to perform HLS IP synthesis and implementation
99
# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

11-
if [ ! -d "./proj" ]; then
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if [ ! -d "./prj" ]; then
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source vitis_hls_csynth.sh
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fi
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‎scripts_for_xilinx_hls/vitis_hls_killall.sh

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#! /usr/bin/env bash
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3+
#------------------------------------------------------------------------------
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# published as part of https://github.com/pConst/basic_verilog
5+
# Konstantin Pavlov, [email protected]
6+
#------------------------------------------------------------------------------
7+
8+
# Script to open Vitis HLS GUI
9+
# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
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killall vitis_hls
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‎scripts_for_xilinx_hls/vitis_hls_syn.sh

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# Script to perform HLS IP synthesis
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# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
1010

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if [ ! -d "./proj" ]; then
11+
if [ ! -d "./prj" ]; then
1212
source vitis_hls_csynth.sh
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fi
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