Rewritten arst conditions in cdc_strobe.sv

Author: pConst

cdc_strobe.sv

@@ -35,7 +35,7 @@
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
-cdc_strobe_v2 cdc_wr_req (
+cdc_strobe cdc_wr_req (
   .arst( 1'b0 ),
 
   .clk1( clk1 ),
@@ -77,19 +77,22 @@ module cdc_strobe (
   // strb1 edge detector
   // prevents secondary strobe generation in case strb1 is not one-cycle-high
   logic strb1_ed;
-  assign strb1_ed = (~strb1_b && strb1) && ~arst;
-
+  assign strb1_ed = ( ~strb1_b && strb1 );
 
   // 2 bit gray counter, it must NEVER be reset
   logic [1:0] gc_FP_ATTR = '0;
-  always @(posedge clk1) begin
-    if( strb1_ed ) begin
-      gc_FP_ATTR[1:0] <= {gc_FP_ATTR[0],~gc_FP_ATTR[1]}; // incrementing counter
+  always @(posedge clk1 or posedge arst) begin
+    if( arst ) begin
+      // nop
+    end else begin
+      if( strb1_ed ) begin
+        gc_FP_ATTR[1:0] <= {gc_FP_ATTR[0],~gc_FP_ATTR[1]}; // incrementing counter
+      end
     end
   end
 
   // buffering counter value on clk2
-  // gray counter does not need a synchronizer
+  // gray counter doesnt need a synchronizer
   logic [1:0][1:0] gc_b = '0;
   always @(posedge clk2 or posedge arst) begin
     if( arst ) begin
@@ -102,7 +105,7 @@ module cdc_strobe (
   end
 
   // gray_bit_b edge detector
-  assign strb2 = (gc_b[1][1:0] != gc_b[0][1:0] ) && ~arst;
+  assign strb2 = ( gc_b[1][1:0] != gc_b[0][1:0] );
 
 
 endmodule