Skip to content

Commit 06c2498

Browse files
pConstpConst
committed
Added xilinx board store
1 parent bdfd79b commit 06c2498

File tree

702 files changed

+160957
-0
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

702 files changed

+160957
-0
lines changed

‎XilinxBoardStore_with_Alveo_cards_support/README.md

+6
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
2+
This is a checkout from original Xilinx repo
3+
https://github.com/Xilinx/XilinxBoardStore commit 78a40f2
4+
5+
This version of board store supports creating Vivado projects for Alveo U200, U250 and U280 accelerators. Future revisions of board store dropped support for Alveo cards for some reason
6+

‎XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/board.xml

+80
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
2+
<board schema_version="2.0" vendor="em.avnet.com" name="minized" display_name="MiniZed" url="http://www.minized.org" preset_file="preset.xml" >
3+
<images>
4+
<image name="minized.jpg" display_name="MiniZed" sub_type="board">
5+
<description>MiniZed Board File Image</description>
6+
</image>
7+
</images>
8+
<compatible_board_revisions>
9+
<revision id="0">1.0</revision>
10+
</compatible_board_revisions>
11+
<file_version>1.2</file_version>
12+
<description>MiniZed</description>
13+
<components>
14+
<component name="part0" display_name="MiniZed" type="fpga" part_name="xc7z007sclg225-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://www.minized.org">
15+
<interfaces>
16+
<interface mode="master" name="pl_sw_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="pl_sw_1bit" preset_proc="pl_sw_1bit_preset">
17+
<description>1 DIP switch</description>
18+
<preferred_ips>
19+
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
20+
</preferred_ips>
21+
<port_maps>
22+
<port_map logical_port="TRI_I" physical_port="pl_sw_1bit_tri_i" dir="in">
23+
<pin_maps>
24+
<pin_map port_index="0" component_pin="pl_sw_1bit_tri_i"/>
25+
</pin_maps>
26+
</port_map>
27+
</port_maps>
28+
</interface>
29+
<interface mode="master" name="pl_led_r" type="xilinx.com:interface:gpio_rtl:1.0" of_component="pl_led_r" preset_proc="pl_led_r_preset">
30+
<description>Red LED</description>
31+
<preferred_ips>
32+
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
33+
</preferred_ips>
34+
<port_maps>
35+
<port_map logical_port="TRI_O" physical_port="pl_led_r_tri_o" dir="out">
36+
<pin_maps>
37+
<pin_map port_index="0" component_pin="pl_led_r_tri_o"/>
38+
</pin_maps>
39+
</port_map>
40+
</port_maps>
41+
</interface>
42+
<interface mode="master" name="pl_led_g" type="xilinx.com:interface:gpio_rtl:1.0" of_component="pl_led_g" preset_proc="pl_led_g_preset">
43+
<description>Green LED</description>
44+
<preferred_ips>
45+
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
46+
</preferred_ips>
47+
<port_maps>
48+
<port_map logical_port="TRI_O" physical_port="pl_led_g_tri_o" dir="out">
49+
<pin_maps>
50+
<pin_map port_index="0" component_pin="pl_led_g_tri_o"/>
51+
</pin_maps>
52+
</port_map>
53+
</port_maps>
54+
</interface>
55+
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
56+
</interface>
57+
</interfaces>
58+
</component>
59+
<component name="pl_sw_1bit" display_name="pl_sw_1bit" type="chip" sub_type="switch" major_group="gpio"/>
60+
<component name="pl_led_g" display_name="pl_led_g" type="chip" sub_type="led" major_group="gpio"/>
61+
<component name="pl_led_r" display_name="pl_led_r" type="chip" sub_type="led" major_group="gpio"/>
62+
<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
63+
</components>
64+
<jtag_chains>
65+
<jtag_chain name="chain1">
66+
<position name="0" component="part0"/>
67+
</jtag_chain>
68+
</jtag_chains>
69+
<connections>
70+
<connection name="part0_pl_sw_1bit" component1="part0" component2="pl_sw_1bit">
71+
<connection_map name="part0_pl_sw_1bit_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
72+
</connection>
73+
<connection name="part0_pl_led_g" component1="part0" component2="pl_led_g">
74+
<connection_map name="part0_pl_led_g_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
75+
</connection>
76+
<connection name="part0_pl_led_r" component1="part0" component2="pl_led_r">
77+
<connection_map name="part0_pl_led_r_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
78+
</connection>
79+
</connections>
80+
</board>

‎XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/minized.jpg

472 KB
Loading

‎XilinxBoardStore_with_Alveo_cards_support/boards/Avnet/minized/1.2/part0_pins.xml

+8
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
2+
<part_info part_name="xc7z007sclg225-1">
3+
<pins>
4+
<pin index="0" name ="pl_sw_1bit_tri_i" iostandard="LVCMOS33" loc="E11"/>
5+
<pin index="0" name ="pl_led_r_tri_o" iostandard="LVCMOS33" loc="E12"/>
6+
<pin index="0" name ="pl_led_g_tri_o" iostandard="LVCMOS33" loc="E13"/>
7+
</pins>
8+
</part_info>

0 commit comments

Comments
 (0)