sidecar-b compiles

Author: hawkw

app/sidecar/base.toml

@@ -105,7 +105,6 @@ task-slots = ["sys", "packrat", { seq = "sequencer" }, "jefe"]
 [tasks.control_plane_agent]
 name = "task-control-plane-agent"
 priority = 7
-max-sizes = {flash = 142900, ram = 65536 }
 # This is a big number -- do we need to tune this?
 stacksize = 12000
 start = true

drv/fpga-api/src/lib.rs

@@ -368,7 +368,7 @@ impl FpgaUserDesign {
         value: T,
     ) -> Result<(), FpgaError>
     where
-        T: IntoBytes,
+        T: IntoBytes + Immutable,
     {
         self.write_bytes(op, addr, value.as_bytes())
     }

drv/ignition-api/src/lib.rs

@@ -644,6 +644,8 @@ impl From<TransceiverEvents> for u8 {
     FromPrimitive,
     ToPrimitive,
     IntoBytes,
+    Immutable,
+    KnownLayout,
 )]
 #[repr(u8)]
 pub enum TransceiverSelect {

drv/monorail-api/src/lib.rs

@@ -251,7 +251,7 @@ pub struct PhyStatus {
     zerocopy::IntoBytes,
     zerocopy::FromBytes,
     zerocopy::Immutable,
-    KnownLayout,
+    zerocopy::KnownLayout,
 )]
 #[repr(C)]
 pub struct MacTableEntry {

drv/sidecar-front-io/src/phy_smi.rs

@@ -7,7 +7,10 @@ use core::cell::Cell;
 use crate::{Addr, Reg};
 use drv_fpga_api::{FpgaError, FpgaUserDesign, WriteOp};
 use vsc85xx::{PhyRw, VscError};
-use zerocopy::{byteorder, FromBytes, IntoBytes, Unaligned, U16};
+use zerocopy::{
+    byteorder::little_endian, FromBytes, Immutable, IntoBytes, KnownLayout,
+    Unaligned,
+};
 
 #[derive(Copy, Clone, Eq, Debug, PartialEq)]
 pub enum PhyOscState {
@@ -159,7 +162,7 @@ impl PhySmi {
         value: u16,
     ) -> Result<(), FpgaError> {
         let request = SmiWriteRequest {
-            wdata: U16::new(value),
+            wdata: little_endian::U16::new(value),
             phy,
             reg,
             ctrl: Reg::VSC8562::PHY_SMI_CTRL::RW
@@ -188,26 +191,26 @@ impl PhyRw for PhySmi {
     }
 }
 
-#[derive(IntoBytes, FromBytes, Unaligned)]
+#[derive(IntoBytes, FromBytes, Unaligned, Immutable, KnownLayout)]
 #[repr(C)]
 struct SmiWriteRequest {
-    wdata: U16<byteorder::LittleEndian>,
+    wdata: little_endian::U16,
     phy: u8,
     reg: u8,
     ctrl: u8,
 }
 
-#[derive(IntoBytes, FromBytes, Unaligned)]
+#[derive(IntoBytes, FromBytes, Unaligned, Immutable, KnownLayout)]
 #[repr(C)]
 struct SmiReadRequest {
     phy: u8,
     reg: u8,
     ctrl: u8,
 }
 
-#[derive(IntoBytes, FromBytes, Unaligned, Default)]
+#[derive(IntoBytes, FromBytes, Unaligned, Default, Immutable, KnownLayout)]
 #[repr(C)]
 struct SmiReadData {
     status: u8,
-    rdata: U16<byteorder::LittleEndian>,
+    rdata: little_endian::U16,
 }

drv/sidecar-front-io/src/transceivers.rs

@@ -7,7 +7,10 @@ use drv_fpga_api::{FpgaError, FpgaUserDesign, ReadOp, WriteOp};
 use drv_transceivers_api::{ModuleStatus, TransceiversError, NUM_PORTS};
 use transceiver_messages::ModuleId;
 use userlib::UnwrapLite;
-use zerocopy::{byteorder, FromBytes, IntoBytes, Unaligned, U16};
+use zerocopy::{
+    byteorder::little_endian, FromBytes, Immutable, IntoBytes, KnownLayout,
+    Unaligned,
+};
 
 // The transceiver modules are split across two FPGAs on the QSFP Front IO
 // board, so while we present the modules as a unit, the communication is
@@ -732,7 +735,7 @@ impl Transceivers {
             let mask = fpga_masks.get(fpga_index);
             if !mask.is_empty() {
                 let fpga = self.fpga(fpga_index);
-                let wdata: U16<byteorder::LittleEndian> = U16::new(mask.get());
+                let wdata = little_endian::U16::new(mask.get());
                 // mark that an error occurred so we can modify the success mask
                 if fpga.write(op, addr, wdata).is_err() {
                     error |= match fpga_index {
@@ -832,11 +835,11 @@ impl Transceivers {
     /// success: we were able to read from the FPGA
     /// error: an `FpgaError` occurred
     pub fn get_module_status(&self) -> (ModuleStatus, ModuleResultNoFailure) {
-        let ldata: Option<[U16<byteorder::LittleEndian>; 8]> = self
+        let ldata: Option<[little_endian::U16; 8]> = self
             .fpga(FpgaController::Left)
             .read(Addr::QSFP_POWER_EN0)
             .ok();
-        let rdata: Option<[U16<byteorder::LittleEndian>; 8]> = self
+        let rdata: Option<[little_endian::U16; 8]> = self
             .fpga(FpgaController::Right)
             .read(Addr::QSFP_POWER_EN0)
             .ok();
@@ -877,7 +880,8 @@ impl Transceivers {
         let error = !success;
 
         (
-            ModuleStatus::read_from(status_masks.as_bytes()).unwrap_lite(),
+            ModuleStatus::read_from_bytes(status_masks.as_bytes())
+                .unwrap_lite(),
             ModuleResultNoFailure::new(success, error).unwrap_lite(),
         )
     }
@@ -988,7 +992,7 @@ impl Transceivers {
             let request = TransceiversI2CRequest {
                 reg,
                 num_bytes,
-                mask: U16::new(fpga_masks.left.0),
+                mask: little_endian::U16::new(fpga_masks.left.0),
                 op: i2c_op as u8,
             };
 
@@ -1005,7 +1009,7 @@ impl Transceivers {
             let request = TransceiversI2CRequest {
                 reg,
                 num_bytes,
-                mask: U16::new(fpga_masks.right.0),
+                mask: little_endian::U16::new(fpga_masks.right.0),
                 op: i2c_op as u8,
             };
             if self
@@ -1243,7 +1247,7 @@ impl Transceivers {
 // The I2C control register looks like:
 // [2..1] - Operation (0 - Read, 1 - Write, 2 - RandomRead)
 // [0] - Start
-#[derive(Copy, Clone, Debug, IntoBytes)]
+#[derive(Copy, Clone, Debug, IntoBytes, Immutable, KnownLayout)]
 #[repr(u8)]
 pub enum TransceiverI2COperation {
     Read = 0x01,
@@ -1258,11 +1262,11 @@ impl From<TransceiverI2COperation> for u8 {
     }
 }
 
-#[derive(IntoBytes, FromBytes, Unaligned)]
+#[derive(IntoBytes, FromBytes, Immutable, KnownLayout, Unaligned)]
 #[repr(C)]
 pub struct TransceiversI2CRequest {
     reg: u8,
     num_bytes: u8,
-    mask: U16<byteorder::LittleEndian>,
+    mask: little_endian::U16,
     op: u8,
 }

drv/sidecar-mainboard-controller/src/fan_modules.rs

@@ -6,11 +6,21 @@ use crate::{Addr, MainboardController, Reg};
 use bitfield::bitfield;
 use drv_fpga_api::{FpgaError, FpgaUserDesign, WriteOp};
 use userlib::FromPrimitive;
-use zerocopy::{FromBytes, IntoBytes};
+use zerocopy::{FromBytes, Immutable, IntoBytes, KnownLayout};
 
 use Reg::FAN0_STATE;
 bitfield! {
-    #[derive(Copy, Clone, PartialEq, Eq, FromPrimitive, IntoBytes, FromBytes)]
+    #[derive(
+        Copy,
+        Clone,
+        PartialEq,
+        Eq,
+        FromPrimitive,
+        IntoBytes,
+        FromBytes,
+        Immutable,
+        KnownLayout
+    )]
     #[repr(C)]
     pub struct FanModuleStatus(u8);
     pub enable, set_enable: FAN0_STATE::ENABLE.trailing_zeros() as usize;
@@ -41,7 +51,17 @@ pub enum FanModulePowerState {
 ///
 /// The SP applies control at the individual fan level. Power control and
 /// status, module presence, and module LED control exist at the module level.
-#[derive(Copy, Clone, Debug, PartialEq, Eq, FromPrimitive, IntoBytes)]
+#[derive(
+    Copy,
+    Clone,
+    Debug,
+    PartialEq,
+    Eq,
+    FromPrimitive,
+    IntoBytes,
+    Immutable,
+    KnownLayout,
+)]
 #[repr(u8)]
 pub enum FanModuleIndex {
     Zero = 0,

drv/sidecar-mainboard-controller/src/ignition.rs

@@ -5,7 +5,7 @@
 use crate::{Addr as MainboardControllerAddr, MainboardController};
 use drv_fpga_api::{FpgaError, FpgaUserDesign, WriteOp};
 use drv_ignition_api::{Addr as IgnitionPageAddr, *};
-use zerocopy::{FromBytes, IntoBytes};
+use zerocopy::{FromBytes, Immutable, IntoBytes};
 
 pub struct IgnitionController {
     fpga: FpgaUserDesign,
@@ -49,7 +49,7 @@ impl IgnitionController {
         value: T,
     ) -> Result<(), FpgaError>
     where
-        T: IntoBytes + FromBytes,
+        T: IntoBytes + FromBytes + Immutable,
     {
         self.fpga
             .write(WriteOp::Write, self.port_addr(port, offset), value)
@@ -64,7 +64,7 @@ impl IgnitionController {
         value: T,
     ) -> Result<(), FpgaError>
     where
-        T: IntoBytes + FromBytes,
+        T: IntoBytes + FromBytes + Immutable,
     {
         self.fpga.write(op, self.port_addr(port, offset), value)
     }